AD5667-RBRMZ-2 datasheet(21/30 Pages) AD

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Preliminary Technical Data

AD5627R/AD5647R/AD5667R, AD5627/AD5667

Rev. PrA. | Page 21 of 30

The AD5627R/AD5647R/AD5667R, AD5627/AD5667 support

standard (100 kHz), fast (400 kHz), and high speed (3.4 MHz)

data transfer modes. High-speed operation is only available on

selected models. See the Ordering Information on the back

page for a full list of models. Support is not provided for 10-bit

addressing and general call addressing.

The AD5627R/AD5647R/AD5667R, AD5627/AD5667 each

have a 7-bit slave address. The two LSBs are set by the state of

the ADDR address pin, which determines the state of the A0

and A1 address bits.

The ADDR pin is three-state, and can be set as shown in Table

8 to give three different addresses.

Table 8. ADDR Pin Settings

ADDR PIN CONNECTION

VDD

No Connection

GND

The 2-wire serial bus protocol operates as follows:

1. The master initiates data transfer by establishing a start

condition, which is when a high-to-low transition on the

SDA line occurs while SCL is high. The following byte is the

address byte, which consists of the 7-bit slave address. The

slave address corresponding to the transmitted address

responds by pulling SDA low during the ninth clock pulse

(this is termed the acknowledge bit). At this stage, all other

devices on the bus remain idle while the selected device waits

for data to be written to, or read from, its shift register.

2. Data is transmitted over the serial bus in sequences of nine clock

pulses (eight data bits followed by an acknowledge bit). The

transitions on the SDA line must occur during the low period of

SCL and remain stable during the high period of SCL.

3. When all data bits have been read or written, a stop

condition is established. In write mode, the master pulls the

SDA line high during the 10th clock pulse to establish a

stop condition. In read mode, the master issues a no

acknowledge for the ninth clock pulse (that is, the SDA line

remains high). The master then brings the SDA line low

before the 10th clock pulse, and then high during the 10th

clock pulse to establish a stop condition.

R/W

SCL

SDA

DB23 D B22 DB2 1 D B20 DB19 DB 18 D B17 DB1 6

ACK. BY

AD56x7

START BY

MASTER

FRAME 1

SLAVE ADDRESS

FRAME 2

COMMAND BYTE

ACK. BY

AD56x7

DB7

DB6

DB5

D B4

D B3

D B2

DB 1

DB0

ACK. BY

AD56x7

STOP BY

MASTER

SCL

(CONTINUED)

SDA

(CONTINUED)

DB15 DB14 DB 13 DB12 DB 11 DB10 DB 9

DB8

ACK. BY

AD56x7

FRAME 3

MOST SIGNIFICANT

DATA BYTE

FRAME 4

LEAST SIGNIFICANT

DATA BYTE

Figure 52. I2C Write Operation

WRITE OPERATION

When writing to the AD5627R/AD5647R/AD5667R,

AD5627/AD5667, the user must begin with a start command

followed by an address byte (R/W = 0), after which the DAC

acknowledges that it is prepared to receive data by pulling SDA

low. The AD5667 requires two bytes of data for the DAC and a

command byte that controls various DAC functions. Three

bytes of data must therefore written to the DAC, the command

byte followed by the most significant data byte and the least

significant data byte, as shown in Figure 52. All these data

bytes are acknowledged by the AD5627R/AD5647R/AD5667R,

AD5627/AD5667. A stop condition follows.

READ OPERATION

When reading data back from the

AD5627R/AD5647R/AD5667R, AD5627/AD5667, the user

begins with a start command followed by an address byte (R/W

= 1), after which the DAC acknowledges that it is prepared to

transmit data by pulling SDA low. Two bytes of data are then

read from the DAC, which are both acknowledged by the

master as shown in Figure 53. A stop condition follows.

Note that the only data that can be read back from the AD56x7

is the contents of the input shift register (see section on Control

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