AD5667-RBRMZ-2 datasheet(22/30 Pages) AD

22 / 30 page

AD5627R/AD5647R/AD5667R, AD5627/AD5667

Preliminary Technical Data

Rev. PrA. | Page 22 of 30

R/W

SCL

SDA

DB23 DB 22 D B21 DB 20 DB1 9 DB 18 D B17 DB 16

ACK. BY

MASTER

START BY

MASTER

FRAME 1

SLAVE ADDRESS

FRAME 2

COMMAND BYTE

ACK. BY

AD56x7

DB7

D B 6

DB 5

D B4

D B3

DB 2

D B1

DB 0

NO ACK.

STOP BY

MASTER

SCL

(CONTINUED)

SDA

(CONTINUED)

DB15 DB14 D B13 DB12 DB11 DB1 0 DB9

DB8

ACK. BY

MASTER

FRAME 3

MOST SIGNIFICANT

DATA BYTE

FRAME 4

LEAST SIGNIFICANT

DATA BYTE

Figure 53. I2C Read Operation

HIGH SPEED MODE

Some models offer high-speed serial communication with a

clock frequency of 3.4 MHz. See the Ordering Information on

the back page for a full list of models.

High speed mode communication commences after the master

addresses all devices connected to the bus with the Master Code

00001XXX to indicate that a high speed mode transfer is to

begin. No device connected to the bus is permitted to

acknowledge the high speed master code, therefore, the code is

followed by a no acknowledge. The master must then issue a

repeated start followed by the device address. The selected

device then acknowledges its address. All devices continue to

operate in high speed mode until the master issues a stop

condition. When the stop condition is issued, the devices

return to standard/fast mode. The part will also exit high speed

mode when

CLR is activated.

SCL

SDA

START BY

MASTER

HS-MODE MASTER CODE

SERIAL BUS ADDRESS BYTE*

ACK. BY

AD56x7

NACK

R/W

FAST MODE

HIGH-SPEED MODE

Figure 54. Placing the AD56x7 in High-Speed Mode

MULTIPLE BYTE WRITE

Once an AD56x7 has been addressed, one or more three-byte

blocks of command and data can be sent to the device, until a

stop condition is received. The device must then be re-

addressed. For this type of operation, the “S” bit in the

command byte is set to zero.

For some types of application such as waveform generation, it

may be required to update a DAC or DACs as fast as possible

without changing the command byte. In this case the “S” bit in

the initial command byte is set to 1. This sets the command

parameters for all subsequent data. Thereafter, multiple two-

byte blocks of data high byte and data low byte can be sent,

without sending a further command byte, until a stop condition

is received.

The “S” bit is only active in the first command byte following

the device slave address. Therefore, even if the “S” bit is 0 and

three-byte blocks of command and data are being sent, it is not

possible to alter the multi-byte mode by changing the “S” bit to

1 “on-the-fly” during any subsequent command byte.

STOP

LEAST SIGNIFICANT

DATA BYTE

MOST SIGNIFICANT

DATA BYTE

COMMAND

BYTE

BLOCK 1

S=0

SLAVE

ADDRESS

LEAST SIGNIFICANT

DATA BYTE

MOST SIGNIFICANT

DATA BYTE

COMMAND

BYTE

BLOCK 2

S=0

LEAST SIGNIFICANT

DATA BYTE

MOST SIGNIFICANT

DATA BYTE

COMMAND

BYTE

BLOCK n

S=0

Figure 55. Multiple Block Write With Command Byte in Each Block (S=0)

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