AD5667-RBRMZ-2 datasheet(25/30 Pages) AD

25 / 30 page

Preliminary Technical Data

AD5627R/AD5647R/AD5667R, AD5627/AD5667

Rev. PrA. | Page 25 of 30

XXX

COMMAND

DAC ADDRESS

(DON’T CARE)

DB15 DB14 DB13 DB12 DB11 DB10

DB9

DB8

DB7

DB6

DB5

DB4

DB2

DB3

DB1

DB0

DON’T CARE

DON’T

CARE

DACA

DACB

DON’T CARE

DAC SELECT

(0 = LDAC PIN ENABLED)

RES

Figure 60. LDAC Setup Command

LDAC PIN

Updating of the DAC registers may also be controlled by the

LDAC pin. This can operate either synchronously or

asynchronously. Whenever LDAC is brought low, the DAC

registers are updated with the contents of the input registers. If

LDAC is held low, update takes place synchronously at the end

of every write operation.

Which DAC registers are updated when LDAC is brought low

is determined by the LDAC setup command. It is the inverse of

those registers that are set to update at the end of write. If one

of bits DB1 or DB0 is a 0, then the corresponding DAC is

updated when LDAC is taken low. If it is a 1, the DAC is

updated at the end of a write operation. This allows one DACs

to be updated automatically at the end of write, and the other to

be updated asynchronously using the LDAC pin.

If LDAC is permanently held low for synchronous update, then

both DACs will be updated irrespective of the DAC address in

the write command or the bit settings in the LDAC setup

command.

This is because the DAC whose bit is 0 in

LDAC setup will be updated due to the LDAC pin being low,

and the DACs whose bit is 1 will be updated due to the LDAC

setup command.

If DAC update is to be controlled solely by the write and LDAC

setup commands, the LDAC pin must be tied high (or use the

10-pin device which does not have this pin). If DAC update is

to be controlled solely by the LDAC pin, then use only

command 000 and set DB3 to DB0 to 0 in the LDAC setup

command.

These parts each contain an extra feature whereby a DAC

updated since the last time LDAC was brought low. Normally,

when LDAC is brought low, the DAC registers are filled with

the contents of the input registers. In the case of the AD56X7,

the DAC register updates only if the input register has changed

since the last time the DAC register was updated, thereby

removing unnecessary digital crosstalk.

POWER-DOWN MODES

XXX

COMMAND

DAC ADDRESS

(DON’T CARE)

DB15 DB14 DB13 DB12 DB11 DB10

DB9

DB8

DB7

DB6

DB5

DB4

DB2

DB3

DB1

DB0

DON’T CARE

DON’T

CARE

DACA

PD1

PD0

DACB

DON’T CARE

POWER

DOWN MODE

DAC SELECT

(1 = DAC SELECTED)

RES

DON’T CARE

Figure 61. Power Up/down Command

Command 100 is the power up/down function. The parameters

of the power up/down function are programmed by bits DB5

and DB4. This defines the output state of the DAC amplifier, as

shown in Table 11. Bits DB3 to DB0 determine to which DAC

or DACs the power up/down command is applied. Setting the

one of these bits to 1 applies the power up/down state defined

by DB5 and DB4 to the corresponding DAC. If a bit is 0, the

state of the DAC is unchanged.

In power-down mode, the amplifier is disconnected from the

output pin, and the output pin is either open-circuit or

connected ground via a 10kΩ or 100kΩ resistor, depending on

the setting of DB5 and DB4.

Table 11. Modes of Operation for the

AD5627R/AD5647R/AD5667R, AD5627/AD5667

DB5

DB4

Operating Mode

Normal operation

Power-down modes

1 kΩ pulldown to GND

100 kΩ pulldown to GND

Three-state, high impedance

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