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AD5667-RBRMZ-2 数据表(PDF) 24 Page - Analog Devices

部件名 AD5667-RBRMZ-2
功能描述  Dual, 12-/14-/16-Bit nanoDACs with 5ppm/C On-Chip Ref, I2C Interface
PDF  30 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

AD5667-RBRMZ-2 数据表(HTML) 24 Page - Analog Devices

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AD5627R/AD5647R/AD5667R, AD5627/AD5667
Preliminary Technical Data
Rev. PrA. | Page 24 of 30
C2
C1
C0
A2
A1
A0
D11
D10
D9
D8
D7
D6
D5
D4
D2
D3
D1
D0
S
R
COMMAND
DAC ADDRESS
DAC DATA
DAC OR COMMAND DATA
COMMAND BYTE
DATA HIGH BYTE
DATA LOW BYTE
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
X
X
X
X
Figure59. AD5627R/AD5627 Input Shift Register (12-Bit DAC)
WRITE COMMANDS AND LDAC
Table 9.
Command Definition
C2
C1
C0
Command
0
0
0
Write to input register n
0
0
1
Update DAC register n
0
1
0
Write to input register n, update all (software
LDAC)
0
1
1
Write to and update DAC channel n
1
0
0
Power up/power down
1
0
1
Reset
1
1
0
LDAC register setup
1
1
1
Internal reference setup (on/off )
Table 9 is the truth table for the command bits. The DAC or
DACs on which a command is performed is/are defined by n,
which is the DAC address shown in table 10. Some commands
required additional data which is defined in the low data byte.
Table 11. DAC Address Command
A2
A1
A0
ADDRESS (n)
0
0
0
DAC A
0
0
1
DAC B
1
1
1
Both DACs
The AD5627R/AD5647R/AD5667R, AD5627/AD5667 DACs
have double-buffered interfaces consisting of two banks of
registers: input registers and DAC registers. The input registers
are connected directly to the input shift register and the digital
code is transferred to the relevant input register on completion
of a valid write sequence. The DAC registers contain the digital
code used by the resistor strings.
The double-buffered interface is useful if the user requires
simultaneous updating of all DAC outputs. For example, the
user could write to three of the input registers individually and
then write to the remaining input register and, updating both
DAC registers, the outputs will update simultaneously.
The AD56x7 has a powerful set of commands for writing to and
updating the DACs. There is also has a hardware load DAC
(LDAC) pin. It is important to understand how these
commands and the LDAC pin operate and interact with each
other, in order to ensure that the desired result is obtained.
The first four commands are used for writing to and updating
the DACs.
Command 000 writes to input register n, without updating the
DAC registers, where n is the input register defined by the A2 ---
A0 bits in the command byte. Depending on the value of A2 ---
A0, this can be any one of the input registers or both input
registers, as defined b y the DAC address.
Command 001 does not write to the input registers, but
(depending on the value of A2 --- A0) updates a DAC register or
both DAC registers.
Command 010 writes to input register n, and updates both
DAC registers.
Command 011 writes to input register n and updates DAC
register n. Since n can be all DACs (A2 --- A0 = 111) commands
010 and 011 are equivalent if A2 --- A0 = 111.
LDAC SETUP
In addition to the write commands, the LDAC setup command
(110) can also determine which DACs are updated at the end of
a write operation (this command does not update the DACs
when it is implemented). It also affects the operation of the
LDAC pin on the 14-pin device (see below). When this
command is sent to the device, data bits DB1 and DB0
determine which of DAC registers B and A are updated at the
end of write. If a bit is set to 1, the corresponding DAC is
updated. Note that, during the LDAC setup command, the
DAC address bits A2 – A0 are ignored. It is only DB1 and DB0
that determine which DAC will be updated.
As far as DAC updating is concerned, the write command and
the LDAC setup command are combined (OR’d together).
For example, if the LDAC setup command is set to update
DACs B, and command 011 is sent to write to and update DAC
A, then DAC A will be written to, but DACs A and B will be
updated.



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