AD5667-RBRMZ-2 datasheet(20/30 Pages) AD

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AD5627R/AD5647R/AD5667R, AD5627/AD5667

Preliminary Technical Data

Rev. PrA. | Page 20 of 30

THEORY OF OPERATION

D/A SECTION

The AD5627R/AD5647R/AD5667R, AD5627/AD5667 DACs

are fabricated on a CMOS process. The architecture consists of

a string DAC followed by an output buffer amplifier. Figure 50

shows a block diagram of the DAC architecture.

DAC

REF (+)

RESISTOR

STRING

REF (-)

GND

OUTPUT

AMPLIFIER

GAIN = +2

VOUT

VDD

Figure 50. DAC Architecture

Because the input coding to the DAC is straight binary, the ideal

output voltage when using an external reference is given by

⎟

⎠

⎞

⎜

⎝

⎛

REFIN

OUT

The ideal output voltage when using the internal reference is

given by

⎟

⎠

⎞

⎜

⎝

⎛

REFOUT

OUT

where:

D is the decimal equivalent of the binary code that is loaded to

the DAC register:

0 to 4095 for AD5627R/AD5627 (12 bit).

0 to 16,383 for AD5647R (14 bit).

0 to 65,535 for AD5667R/AD5667 (16 bit).

N is the DAC resolution.

RESISTOR STRING

The resistor string is shown in Figure 51. It is simply a string of

resistors, each of value R. The code loaded to the DAC register

determines at which node on the string the voltage is tapped off

to be fed into the output amplifier. The voltage is tapped off by

closing one of the switches connecting the string to the

amplifier. Because it is a string of resistors, it is guaranteed

monotonic.

OUTPUT AMPLIFIER

The output buffer amplifier can generate rail-to-rail voltages on

its output, which gives an output range of 0 V to VDD. It can drive

a load of 2 kΩ in parallel with 1000 pF to GND. The source and

sink capabilities of the output amplifier can be seen in Figure and

Figure. The slew rate is 1.8 V/µs with a ¼ to ¾ full-scale settling

time of 7 µs.

TO OUTPUT

AMPLIFIER

Figure 51. Resistor String

INTERNAL REFERENCE

The AD5627R/AD5647R/AD5667R feature an on-chip

reference. Versions without the –R suffix require an external

reference. The on-chip reference is off at power-up and is

enabled via a write to a control register. See the Internal

Reference Setup section for details.

Versions packaged in 10-lead LFCSP package have a 1.25 V

reference, giving a full scale output of 2.5 V. These parts can be

operated with a VDD supply of 2.7V to 5.5V. Versions packaged

in 10-lead MSOP package have a 2.5 V reference, giving a full-

scale output of 5 V. Parts are functional with a VDD supply of

2.7V to 5.5V but for VDD supply of less than 5V, the output will

be clamped to VDD. See the Ordering Information on the back

page for a full list of models. The internal reference associated

with each part is available at the VREFOUT pin.

A buffer is required if the reference output is used to drive

external loads. When using the internal reference, it is

recommended that a 100 nF capacitor is placed between

reference output and GND for reference stability.

EXTERNAL REFERENCE

The VREFIN pin on the AD56x7R allows the use of an external

reference if the application requires it. The default condition of

the on-chip reference is off at power-up. All devices can be

operated from a single 2.7 V to 5.5 V supply.

SERIAL INTERFACE

The AD5627R/AD5647R/AD5667R, AD5627/AD5667 have 2-

wire I2C-compatible serial interfaces (refer to I2C-Bus

Specification, Version 2.1, January 2000, available from Philips

Semiconductor). The AD5627R/AD5647R/AD5667R,

AD5627/AD5667 can be connected to an I2C bus as a slave

device, under the control of a master device. See Figure 2 for a

timing diagram of a typical write sequence.

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