TAS5036APFCRG4 datasheet(29/62 Pages) TI

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Architecture Overview

SLES061B—November 2002—Revised January 2004

TAS5036A

The TAS5036A supports the standard-mode I2C bus operation (100 kHz maximum) and the fast I2C bus

operation (400 kHz maximum). The TAS5036A performs all I2C operations without I2C wait cycles.

The I2C bus employs two signals, SDA (data) and SCL (clock), to communicate between integrated circuits

in a system. Data is transferred on the bus serially one bit at a time. The address and data are transferred in

byte (8 bit) format with the most significant bit (MSB) transferred first. In addition, each byte transferred on the

bus is acknowledged by the receiving device with an acknowledge bit. Each transfer operation begins with

the master device driving a start condition on the bus and ends with the master device driving a stop condition

on the bus. The bus uses transitions on the data terminal (SDA) while the clock is high to indicate start and

stop conditions. A high-to-low transition on SDA indicates a start, and a low-to-high transition indicates a stop.

Normal data bit transitions must occur within the low time of the clock period. These conditions are shown in

Figure 2−13. The master generates the 7-bit slave address and the read/write (R/W) bit to open

communication with another device and then waits for an acknowledge condition. The TAS5036A holds SDA

low during acknowledge clock period to indicate an acknowledgement. When this occurs, the master transmits

the next byte of the sequence. Each device is addressed by a unique 7-bit slave address plus R/W bit (1 byte).

All compatible devices share the same signals via a bidirectional bus using a wired-AND connection. An I2C

external pullup resistor must be used for the SDA and SCL signals to set the high level for the bus.

7 Bit Slave Address

8 Bit Register Address (N)

8 Bit Register Data For

Address (N)

Start

Stop

SDA

SCL

8 Bit Register Data For

Address (N)

Figure 2−13. Typical I2C Sequence

There are no limits on the number of bytes that can be transmitted between start and stop conditions. When

the last word transfers, the master generates a stop condition to release the bus. A generic data transfer

sequence is also shown in Figure 2−13.

The 7-bit address for the TAS5036A is 001101X, where X is a programmable address bit. Using the CS0

terminal on the device, the LSB address bit is programmable to permit two devices to be used in a system.

These two addresses are licensed I2C addresses and do not conflict with other licensed I2C audio devices.

To communicate with the TAS5036A, the I2C master uses 0011010 if CS0 = 0 and 0011011 if CS0 = 1. In

addition to the 7-bit device address, an 8-bit register address is used to direct communication to the proper

Read and write operations to the TAS5036A can be done using single-byte or multiple-byte data transfers.

2.5.1 Single-Byte Write

As shown in Figure 2−14, a single-byte data write transfer begins with the master device transmitting a start

condition followed by the I2C device address and the read/write bit. The read/write bit determines the direction

of the data transfer. For a write data transfer, the read/write bit is 0. After receiving the correct I2C device

address and the read/write bit, the TAS5036A device responds with an acknowledge bit. Next, the master

transmits the address byte or bytes corresponding to the TAS5036A internal memory address being

accessed. After receiving the address byte, the TAS5036A again responds with an acknowledge bit. Next, the

master device transmits the data byte to be written to the memory address being accessed. After receiving

the data byte, the TAS5036A again responds with an acknowledge bit. Finally, the master device transmits

a stop condition to complete the single-byte data write transfer.

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