TAS5036APFCRG4 datasheet(40/62 Pages) TI

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System Procedures for Initialization, Changing Data Rates, and Switching Between Master and Slave Modes

SLES061B—November 2002—Revised January 2004

TAS5036A

Figure 4−5 shows the procedure to change the data rate using the DBSPD terminal and then restore the

RESET is released. This permits the system controller to have as much additional time as necessary to restore

the register settings.

Once the data rate is set, the ERR_RCVRY and MUTE terminal signals are set high and the system

re-initializes.

MCLK

MUTE

Terminal

ERR_RCVRY

Terminal

Change from a 96-kHz data rate

MCLK_IN = 24.576 MHz

Clock unstable during transition.

HIGH and LOW intervals < 20 ns

Change to a 48-kHz data rate

MCLK_IN = 12.288 MHz

Volume Ramp

Up 120 ms

Volume Ramp

Down 60 ms

ERR_RCVRY can be set at

any time within this interval

Wait a minimum of 100

µs after the

LOW to HIGH transition of RESET

Release ERR_RCVRY and

then MUTE when I2C

registers are programmed

> 5 ms

RESET

Terminal

DBSPD

Terminal

< 2 ms

Wait a minimum of

100

µs to set DBSPD

Restore register

settings via I2C

Figure 4−5. Changing the Data Sample Rate With an Unstable MCLK_IN Using the DBSPD Terminal

Because this sequence employs the RESET terminal, the internal register settings are set to the default

values.

Figure 4−6 shows the procedure to change the data rate using register 0x02 D7 and D6 and then restore the

other register settings. In this example, the ERR_RCVRY terminal is used to hold off system re-initialization

after RESET is released. This permits the system controller to have as much additional time as necessary to

restore the register settings.

Once the data rate is set, the ERR_RCVRY and MUTE terminal signals are set high and the system

re-initializes.

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TAS5036APFCRG4 数据表(PDF) 40 Page - Texas Instruments

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