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TAS5036APFCRG4 数据表(PDF) 18 Page - Texas Instruments

部件名 TAS5036APFCRG4
功能描述  Six Channel Digital Audio PWM Processor
PDF  62 Pages
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制造商  TI [Texas Instruments]
网页  http://www.ti.com
标志 TI - Texas Instruments

TAS5036APFCRG4 数据表(HTML) 18 Page - Texas Instruments

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Architecture Overview
12
SLES061B—November 2002—Revised January 2004
TAS5036A
23
22
SCLK
32 Clks
LRCLK (Note Reversed Phase)
Left Channel
24-Bit Mode
9
8
5
4
1
0
19
18
20-Bit Mode
5
4
1
0
16-Bit Mode
1
0
15
14
MSB
LSB
23
22
SCLK
32 Clks
Right Channel
9
8
5
4
1
0
19
18
5
4
1
0
1
0
15
14
MSB
LSB
2-Channel I2S (Philips Format) Stereo Input
Figure 2−3. I2S 64-Fs Format
2-Channel I2S Stereo Input/Output (24-Bit Transfer Word Size)
23
22
SCLK
24 Clks
LRCLK
Left Channel
24-Bit Mode
20
19
8
7
2
1
19
18
20-Bit Mode
16
15
1
0
16-Bit Mode
1
0
15
14
MSB
LSB
4
3
5
21
4
5
17
13
12
11
23
22
SCLK
24 Clks
Right Channel
20
19
8
7
2
1
19
18
16
15
1
0
1
0
15
14
MSB
LSB
4
3
5
21
4
5
17
13
12
11
0
Figure 2−4. I2S 48-Fs Format
2.1.7.2
Left-Justified Timing
Left-justified (LJ) timing uses LRCLK to define when the data being transmitted is for the left channel and the
right channel. LRCLK is high for the left channel and low for the right channel. A bit clock running at 48 or 64
times Fs is used to clock in the data. The first bit of data appears on the data lines at the same time that LRCLK
toggles. The data is written MSB first and is valid on the rising edge of the bit clock. The TAS5036A masks
unused trailing data bit positions. Master mode only supports a 64 times Fs bit clock.



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