TAS5036APFCRG4 datasheet(34/62 Pages) TI

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Serial Control Interface Register Definitions

SLES061B—November 2002—Revised January 2004

TAS5036A

3.6

Automute Delay Register (0x05)

Table 3−7. Automute Delay Register

FUNCTION

Reserved

Set automute delay at 5 ms

Set automute delay at 10 ms

Set automute delay at 15 ms

Set automute delay at 20 ms

Set automute delay at 25 ms

Set automute delay at 30 ms

Set automute delay at 35 ms

Set automute delay at 40 ms

Set automute delay at 45 ms

Set automute delay at 50 ms

3.7

DC-Offset Control Registers (0x06−0x0B)

Channels 1, 2, 3, 4, 5, and 6 are mapped into (0x06, 0x07, 0x08, 0x09, 0x0A, and 0x0B).

Table 3−8. DC-Offset Control Registers

FUNCTION

Maximum correction for positive dc offset (–1.56% FS)

No dc-offset correction

Maximum correction for negative dc offset (1.56% FS)

3.8

Interchannel Delay Registers (0x0C−0x11)

Channels 1, 2, 3, 4, 5, and 6 are mapped into (0x0C, 0x0D, 0x0E, 0x0F, 0x10, and 0x11).

The first channel delay is set at 0. Each subsequent channel has a default value that is 76 DCLKs larger than

the preceding channel.

Table 3−9. Six Interchannel Delay Registers

FUNCTION

Minimum absolute delay, 0 DCLK cycles, default for channel 1

Default for channel 2

Default for channel 3

Default for channel 4

Default for channel 5

Default for channel 6

Maximum absolute delay, 255 DCLK cycles

3.9

ABD Delay Register (0x12)

Table 3−10. ABD Delay Register

FUNCTION

Reserved

Minimum ABD delay, 0 DLCK cycles

Default ABD delay, 17 DLCK cycles

Maximum ABD delay, 31 DLCK cycles

TAS5036APFCRG4 数据表(PDF) 34 Page - Texas Instruments

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