TAS5036APFCRG4 datasheet(39/62 Pages) TI

39 / 62 page

System Procedures for Initialization, Changing Data Rates, and Switching Between Master and Slave Modes

SLES061B—November 2002—Revised January 2004

TAS5036A

MCLK

MUTE

Terminal

DBSPD

Terminal

Change from a 96-kHz data rate

MCLK_IN = 24.576 MHz

Clock Transition

Change to a 48-kHz data rate

MCLK_IN = 12.288 MHz

Volume Ramp

Up 42 − 65 ms

> 5 ms

< 2 ms

Volume Ramp

Down 42 − 65 ms

Set within 2 ms

of transition

Figure 4−3. Changing the Data Sample Rate Using the DBSPD Terminal

MCLK

MUTE

Terminal

Change from a 96-kHz data rate

MCLK_IN = 24.576 MHz

Clock Transition

Change to a 48-kHz data rate

MCLK_IN = 12.288 MHz

Volume Ramp

Up 42 − 65 ms

> 5 ms

< 2 ms

Volume Ramp

Down 42 − 65 ms

Set data rate via I2C

ERR_RCVRY

Terminal

Hold ERR_RCVRY LOW to give

additional time to set registers

Figure 4−4. Changing the Data Sample Rate Using the I2C

However, if the master clock input can encounter a high clock or low clock period of less than 20 ns, then

RESET should be applied during this time. There are two recommended control procedures for this case,

depending upon whether the DBSPD terminal or the serial control interface is used. These control sequences

are shown in Figure 4−5 and Figure 4−6.

Because this sequence employs the RESET terminal the internal register settings are set to the default values.

TAS5036APFCRG4 数据表(PDF) 39 Page - Texas Instruments

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TAS5036APFCRG4 数据表(PDF) 39 Page - Texas Instruments

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