STA323W datasheet(68/71 Pages) STMICROELECTRONICS

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User-programmable settings

STA323W

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8.13.1

Thermal warning indicator

If the power stage thermal operating conditions are exceeded, the thermal warning indicator

transmits a signal to the digital logic block to initiate a corrective procedure. This register bit

is set to '0' to indicate a thermal warning and it reverts back to its default state as soon as

the cause of the thermal warning has been corrected.

8.13.2

Fault detect indicator

As soon as the power stage issues a Fault error signal, thereby initiating the Fault recovery

procedure described in Section 8.12, this register bit is set to '0' to indicate the error to the

user. As soon as the fault condition (over-current or thermal) is corrected, this bit is reset

back to its default state.

8.13.3

PLL unlock indicator

Under normal conditions (with the correct clock) the PLL is locked into an internal clocking

frequency. However, if the clock is insufficient or if it is abruptly lost, the PLL lock state is lost

and this information is relayed to the user via setting the PLLUL bit of the Status register to

'1'. As soon as the PLL reverts back to a locked state, this bit is set to '0'.

Table 70.

Thermal warning indicator

Bit

R/W

RST

Name

Description

1RWRAN

0: thermal warning detected

1: normal operation (no thermal warning)

Table 71.

Fault detect indicator

Bit

R/W

RST

Name

Description

FAULT

0: fault issued from the power stage

1: normal operation (no fault)

Table 72.

PLL unlock indicator

Bit

R/W

RST

Name

Description

0PLLUL

0: normal operation (PLL is in a locked state)

1: PLL unlock is detected (due to probable

clock loss)

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