STA323W datasheet(31/71 Pages) STMICROELECTRONICS

31 / 71 page

STA323W

STA323W I2C bus specification

31/71

6.3

Write operation

Following the START condition the master sends a device select code with the RW bit set to

0. The STA323W acknowledges this and then the master writes the internal address byte.

After receiving the internal byte address the STA323W again responds with an

acknowledgement.

6.3.1

Byte write

In the byte write mode the master sends one data byte. This is acknowledged by the

STA323W. The master then terminates the transfer by generating a STOP condition.

6.3.2

Multi-byte write

The multi-byte write modes can start from any internal address. Sequential data bytes are

written to sequential addresses within the STA323W.

The master generates a STOP condition to terminate the transfer.

6.4

Read operation

6.4.1

Current address byte read

Following the START condition the master sends a device select code with the RW bit set

to 1. The STA323W acknowledges this and then responds by sending one byte of data. The

master then terminates the transfer by generating a STOP condition.

Current address multi-byte read

The multi-byte read modes can start from any internal address. Sequential data bytes are

read from sequential addresses within the STA323W. The master acknowledges each data

byte read and then generates a STOP condition to terminate the transfer.

6.4.2

Random address byte read

Following the START condition the master sends a device select code with the RW bit set to

0. The STA323W acknowledges this and then the master writes the internal address byte.

After receiving, the internal byte address the STA323W again responds with an

acknowledgement. The master then initiates another START condition and sends the device

select code with the RW bit set to 1. The STA323W acknowledges this and then responds

by sending one byte of data. The master then terminates the transfer by generating a STOP

condition.

Random address multi-byte read

The multi-byte read modes can start from any internal address. Sequential data bytes are

then read from sequential addresses within the STA323W. The master acknowledges each

data byte read and then generates a STOP condition to terminate the transfer.

STA323W 数据表(PDF) 31 Page - STMicroelectronics

STA323W 数据表(HTML) 31 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71

数据表下载