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AT89C51AC3-RDTIM 数据表(PDF) 67 Page - ATMEL Corporation |
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AT89C51AC3-RDTIM 数据表(HTML) 67 Page - ATMEL Corporation |
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67 / 143 page  67 AT89C51AC3 4383B–8051–01/05 Mode 0 (13-bit Timer) Mode 0 configures Timer 0 as an 13-bit Timer which is set up as an 8-bit Timer (TH0 register) with a modulo 32 prescaler implemented with the lower five bits of TL0 register (see Figure 35). The upper three bits of TL0 register are indeterminate and should be ignored. Prescaler overflow increments TH0 register. Figure 35. Timer/Counter x (x = 0 or 1) in Mode 0 Mode 1 (16-bit Timer) Mode 1 configures Timer 0 as a 16-bit Timer with TH0 and TL0 registers connected in cascade (see Figure 36). The selected input increments TL0 register. Figure 36. Timer/Counter x (x = 0 or 1) in Mode 1 FTx CLOCK TRx TCON reg TFx TCON reg 0 1 GATEx TMOD reg ÷ 6 Overflow Timer x Interrupt Request C/Tx# TMOD reg TLx (5 bits) THx (8 bits) INTx# Tx See the “Clock” section TRx TCON reg TFx TCON reg 0 1 GATEx TMOD reg Overflow Timer x Interrupt Request C/Tx# TMOD reg TLx (8 bits) THx (8 bits) INTx# Tx FTx CLOCK ÷ 6 See the “Clock” section |
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