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AT89C51AC3-RDTIM 数据表(PDF) 34 Page - ATMEL Corporation |
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AT89C51AC3-RDTIM 数据表(HTML) 34 Page - ATMEL Corporation |
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34 / 143 page  34 AT89C51AC3 4383B–8051–01/05 Registers Table 10. PCON Register PCON (S87:h) Power configuration Register Reset Value= XXXX 0000b 76 543 210 -- -- GF1 GF0 PD IDL Bit Number Bit Mnemonic Description 7-4 - Reserved The value read from these bits is indeterminate. Do not set these bits. 3GF1 General Purpose flag 1 One use is to indicate whether an interrupt occurred during normal operation or during Idle mode. 2GF0 General Purpose flag 0 One use is to indicate whether an interrupt occurred during normal operation or during Idle mode. 1PD Power-Down Mode bit Cleared by hardware when an interrupt or reset occurs. Set to activate the Power-Down mode. If IDL and PD are both set, PD takes precedence. 0IDL Idle Mode bit Cleared by hardware when an interrupt or reset occurs. Set to activate the Idle mode. If IDL and PD are both set, PD takes precedence. |
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