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AT89C51AC3-RDTIM 数据表(PDF) 88 Page - ATMEL Corporation

部件名 AT89C51AC3-RDTIM
功能描述  Enhanced 8-bit Microcontroller with 64KB Flash Memory
PDF  143 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
制造商  ATMEL [ATMEL Corporation]
网页  http://www.atmel.com
标志 ATMEL - ATMEL Corporation

AT89C51AC3-RDTIM 数据表(HTML) 88 Page - ATMEL Corporation

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AT89C51AC3
4383B–8051–01/05
When a transmission is in progress a new data can be queued and sent as soon as
transmission has been completed. So it is possible to transmit bytes without latency,
useful in some applications.
The SPTE bit in SPSCR is set as long as the transmission buffer is free. It means that
the user application can write SPDAT with the data to be transmitted until the SPTE
becomes cleared.
Figure 49 shows a queuing transmission in master mode. Once the Byte 1 is ready, it is
immediately sent on the bus. Meanwhile an other byte is prepared (and the SPTE is
cleared), it will be sent at the end of the current transmission. The next data must be
ready before the end of the current transmission.
Figure 49. Queuing Transmission In Master Mode
In slave mode it is almost the same except it is the external master that start the
transmission.
Also, in slave mode, if no new data is ready, the last value received will be the next data
byte transmitted.
MSB
B6
B5
B4
B3
B2
B1
LSB
MOSI
SCK
MSB
B6
B5
B4
B3
B2
B1
LSB
BYTE 1 under transmission
MSB
B6
B5
B4
B3
B2
B1
LSB MSB
B6
B5
B4
B3
B2
B1
LSB
MISO
Data
Byte 1
Byte 2
Byte 3
SPTE
BYTE 2 under transmission



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