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AT89C51AC3-RDTIM 数据表(PDF) 18 Page - ATMEL Corporation |
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AT89C51AC3-RDTIM 数据表(HTML) 18 Page - ATMEL Corporation |
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18 / 143 page  18 AT89C51AC3 4383B–8051–01/05 Registers Table 2. CKCON0 Register CKCON0 (S:8Fh) Clock Control Register Note: 1. This control bit is validated when the CPU clock bit X2 is set; when X2 is low, this bit has no effect. Reset Value = x000 0000b 76 543 210 - WDX2 PCAX2 SIX2 T2X2 T1X2 T0X2 X2 Bit Number Bit Mnemonic Description 7- Reserved The value read from this bits is indeterminate. Do not set this bit. 6WDX2 WatchDog clock (1) Clear to select 6 clock periods per peripheral clock cycle. Set to select 12 clock periods per peripheral clock cycle. 5 PCAX2 Programmable Counter Array clock (1) Clear to select 6 clock periods per peripheral clock cycle. Set to select 12 clock periods per peripheral clock cycle. 4SIX2 Enhanced UART clock (MODE 0 and 2) (1) Clear to select 6 clock periods per peripheral clock cycle. Set to select 12 clock periods per peripheral clock cycle. 3T2X2 Timer2 clock (1) Clear to select 6 clock periods per peripheral clock cycle. Set to select 12 clock periods per peripheral clock cycle. 2T1X2 Timer1 clock (1) Clear to select 6 clock periods per peripheral clock cycle. Set to select 12 clock periods per peripheral clock cycle. 1T0X2 Timer0 clock (1) Clear to select 6 clock periods per peripheral clock cycle. Set to select 12 clock periods per peripheral clock cycle. 0X2 CPU clock Clear to select 12 clock periods per machine cycle (STD mode) for CPU and all the peripherals. Set to select 6 clock periods per machine cycle (X2 mode) and to enable the individual peripherals "X2"bits. |
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