AT89C51AC3-RDTIM datasheet(10/143 Pages) ATMEL

10 / 143 page

AT89C51AC3

4383B–8051–01/05

write the new byte back to the latch. These Read-Modify-Write instructions are directed

to the latch rather than the pin in order to avoid possible misinterpretation of voltage

(and therefore, logic) levels at the pin. For example, a Port bit used to drive the base of

an external bipolar transistor can not rise above the transistor’s base-emitter junction

voltage (a value lower than VIL). With a logic one written to the bit, attempts by the CPU

to read the Port at the pin are misinterpreted as logic zero. A read of the latch rather

than the pins returns the correct logic-one value.

Quasi-Bidirectional Port

Operation

Port 1, Port 2, Port 3 and Port 4 have fixed internal pull-ups and are referred to as

"quasi-bidirectional" Ports. When configured as an input, the pin impedance appears as

logic one and sources current in response to an external logic zero condition. Port 0 is a

"true bidirectional" pin. The pins float when configured as input. Resets write logic one to

all Port latches. If logical zero is subsequently written to a Port latch, it can be returned

to input conditions by a logical one written to the latch.

Note:

Port latch values change near the end of Read-Modify-Write instruction cycles. Output

buffers (and therefore the pin state) update early in the instruction after Read-Modify-

Write instruction cycle.

Logical zero-to-one transitions in Port 1, Port 2, Port 3 and Port 4 use an additional pull-

up (p1) to aid this logic transition (see Figure 4.). This increases switch speed. This

extra pull-up sources 100 times normal internal circuit current during 2 oscillator clock

periods. The internal pull-ups are field-effect transistors rather than linear resistors. Pull-

ups consist of three p-channel FET (pFET) devices. A pFET is on when the gate senses

logical zero and off when the gate senses logical one. pFET #1 is turned on for two

oscillator periods immediately after a zero-to-one transition in the Port latch. A logical

one at the Port pin turns on pFET #3 (a weak pull-up) through the inverter. This inverter

and pFET pair form a latch to drive logical one. pFET #2 is a very weak pull-up switched

on whenever the associated nFET is switched off. This is traditional CMOS switch con-

vention. Current strengths are 1/10 that of pFET #3.

Figure 4. Internal Pull-Up Configurations

Note:

Port 2 p1 assists the logic-one output for memory bus cycles.

READ PIN

INPUT DATA

P1.x

OUTPUT DATA

2 Osc. PERIODS

p1(1)

VCC

P2.x

P3.x

P4.x

AT89C51AC3-RDTIM 数据表(PDF) 10 Page - ATMEL Corporation

AT89C51AC3-RDTIM 数据表(HTML) 10 Page - ATMEL Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载