BS640HD9V datasheet(23/89 Pages) AMD

23 / 89 page

May 10, 2006 27024B3

Am29BDS128H/Am29BDS640H

D A TA

SH EE T

Automatic Sleep Mode

The automatic sleep mode minimizes Flash device

energy consumption. While in asynchronous mode, the

device automatically enables this mode when

addresses remain stable for tACC + 60 ns. The auto-

matic sleep mode is independent of the CE#, WE#, and

OE# control signals. Standard address access timings

provide new data when addresses are changed. While

in sleep mode, output data is latched and always avail-

able to the system. While in synchronous mode, the

device automatically enables this mode when either the

first active CLK level is greater than tACC or the CLK

runs slower than 5 MHz. Note that a new burst opera-

tion is required to provide new data.

ICC6 in the “DC Characteristics” section on page 54

represents the automatic sleep mode current specifica-

tion.

RESET#: Hardware Reset Input

The RESET# input provides a hardware method of

resetting the device to reading array data. When

RESET# is driven low for at least a period of tRP, the

device immediately terminates any operation in

progress, tristates all outputs, resets the configuration

duration of the RESET# pulse. The device also resets

the internal state machine to reading array data. The

operation that was interrupted should be reinitiated

once the device is ready to accept another command

sequence, to ensure data integrity.

Current is reduced for the duration of the RESET#

pulse. When RESET# is held at VSS ± 0.2 V, the device

draws CMOS standby current (ICC4). If RESET# is held

at VIL but not within VSS ± 0.2 V, the standby current will

be greater.

RESET# may be tied to the system reset circuitry. A

system reset would thus also reset the Flash memory,

enabling the system to read the boot-up firmware from

the Flash memory.

If RESET# is asserted during a program or erase oper-

ation, the device requires a time of tREADY (during

Embedded Algorithms) before the device is ready to

read data again. If RESET# is asser ted when a

program or erase operation is not executing, the reset

operation is completed within a time of tREADY (not

during Embedded Algorithms). The system can read

data tRH after RESET# returns to VIH.

Refer to the “AC Characteristics” section on page 68 for

RESET# parameters and to Figure 33, “Reset Tim-

ings,” on page 68 for the timing diagram.

Output Disable Mode

When the OE# input is at VIH, output from the device is

disabled. The outputs are placed in the high imped-

ance state.

Figure 1.

Temporary Sector Unprotect Operation

START

Perform Erase or

Program Operations

RESET# = VIH

Temporary Sector

Unprotect Completed

(Note 2)

RESET# = VID

(Note 1)

Notes:

1. All protected sectors unprotected (If WP# = VIL,

outermost boot sectors will remain protected).

2. All previously protected sectors are protected once

again.

BS640HD9V 数据表(PDF) 23 Page - Advanced Micro Devices

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