数据搜索系统，热门电子元器件搜索
  Chinese  ▼
ALLDATASHEETCN.COM

X  

预览 PDF HTML

BS640HD9V 数据表(PDF) 59 Page - Advanced Micro Devices

部件名 BS640HD9V
功能描述  128 or 64 Megabit (8 M or 4 M x 16-Bit) CMOS 1.8 Volt-only Simultaneous Read/Write, Burst Mode Flash Memory
PDF  89 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
制造商  AMD [Advanced Micro Devices]
网页  http://www.amd.com
标志 AMD - Advanced Micro Devices

BS640HD9V 数据表(HTML) 59 Page - Advanced Micro Devices

Back Button BS640HD9V Datasheet HTML 55Page - Advanced Micro Devices BS640HD9V Datasheet HTML 56Page - Advanced Micro Devices BS640HD9V Datasheet HTML 57Page - Advanced Micro Devices BS640HD9V Datasheet HTML 58Page - Advanced Micro Devices BS640HD9V Datasheet HTML 59Page - Advanced Micro Devices BS640HD9V Datasheet HTML 60Page - Advanced Micro Devices BS640HD9V Datasheet HTML 61Page - Advanced Micro Devices BS640HD9V Datasheet HTML 62Page - Advanced Micro Devices BS640HD9V Datasheet HTML 63Page - Advanced Micro Devices Next Button
Zoom Inzoom in Zoom Outzoom out
 59 / 89 page
background image
May 10, 2006 27024B3
Am29BDS128H/Am29BDS640H
57
D A TA
SH EE T
AC CHARACTERISTICS
Synchronous/Burst Read
Note: Addresses are latched on the first of either the active edge of CLK or the rising edge of AVD#.
Parameter
Description
66 MHz
54 MHz
Unit
JEDEC
Standard
tIACC
Latency (Even address in Reduced wait-state
Handshaking mode)
Max
56
69
ns
tIACC
Latency (Standard Handshaking or Odd
address in Reduced wait-state Handshaking
mode
Max
71
87.5
ns
tBACC
Burst Access Time Valid Clock to Output
Delay
Max
11
13.5
ns
tACS
Address Setup Time to CLK (Note )
Min
4
5
ns
tACH
Address Hold Time from CLK (Note )
Min
6
7
ns
tBDH
Data Hold Time from Next Clock Cycle
Min
3
4
ns
tCR
Chip Enable to RDY Valid
Max
11
13.5
ns
tOE
Output Enable to Output Valid
Max
11
13.5
ns
tCEZ
Chip Enable to High Z
Max
8
10
ns
tOEZ
Output Enable to High Z
Max
8
10
ns
tCES
CE# Setup Time to CLK
Min
4
5
ns
tRDYS
RDY Setup Time to CLK
Min
4
5
ns
tRACC
Ready Access Time from CLK
Max
11
13.5
ns
tAAS
Address Setup Time to AVD# (Note )
Min
4
5
ns
tAAH
Address Hold Time to AVD# (Note )
Min
6
7
ns
tCAS
CE# Setup Time to AVD#
Min
0
ns
tAVC
AVD# Low to CLK
Min
4
5
ns
tAVD
AVD# Pulse
Min
10
12
ns
tACC
Access Time
Max
50
55
ns
tCKA
CLK to access resume
Max
11
13.5
ns
tCKZ
CLK to High Z
Max
8
10
ns
tOES
Output Enable Setup Time
Min
4
5
ns
tRCC
Read cycle for continuous suspend
Max
1
ms



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89


数据表 下载

Go To PDF Page


链接网址



ALLDATASHEET是否为您带来帮助?  [ DONATE ] 

关于 Alldatasheet   |   广告服务   |   联系我们   |   隐私政策   |   数据表链接    |   链接交换   |   制造商名单
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com