BS640HD9V datasheet(61/89 Pages) AMD

61 / 89 page

May 10, 2006 27024B3

Am29BDS128H/Am29BDS640H

D A TA

SH EE T

AC CHARACTERISTICS

Notes:

1. Figure shows total number of wait states set to seven cycles. The total number of wait states can be programmed from two

cycles to seven cycles. Clock is set for active rising edge.

2. If any burst address occurs at a 64-word boundary, two additional clock cycle are inserted, and is indicated by RDY.

3. The device is in synchronous mode.

Figure 18.

Synchronous Burst Mode Read

Note: Figure assumes 7 wait states for initial access and automatic detect synchronous read. D0–D7 in data waveform indicate

the order of data within a given 8-word address range, from lowest to highest. Starting address in figure is the 7th address in

range (A6). See “Requirements for Synchronous (Burst) Read Operation”. The Set Configuration Register command sequence

has been written with A18=1; device will output RDY with valid data.

Figure 19.

8-word Linear Burst with Wrap Around

Da + 1

Da + n

OE#

Data

Addresses

AVD#

RDY

CLK

CE#

tCAS

tAAS

tAVC

tAVD

tAAH

tOE

tRACC

tOEZ

tCEZ

tIACC

tBDH

7 cycles for initial access shown.

Hi-Z

tRDYS

tBACC

tACC

tCR

OE#

Data

Addresses

AVD#

RDY

CLK

CE#

tCES

tACS

tAVC

tAVD

tACH

tOE

tIACC

tBDH

7 cycles for initial access shown.

Hi-Z

tRACC

456

tRDYS

tBACC

tACC

tCR

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