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BS640HD9V 数据表(PDF) 54 Page - Advanced Micro Devices

部件名 BS640HD9V
功能描述  128 or 64 Megabit (8 M or 4 M x 16-Bit) CMOS 1.8 Volt-only Simultaneous Read/Write, Burst Mode Flash Memory
PDF  89 Pages
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制造商  AMD [Advanced Micro Devices]
网页  http://www.amd.com
标志 AMD - Advanced Micro Devices

BS640HD9V 数据表(HTML) 54 Page - Advanced Micro Devices

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52
Am29BDS128H/Am29BDS640H
27024B3 May 10, 2006
D A TA
SH EE T
device will accept additional sector erase commands.
To ensure the command has been accepted, the
system software should check the status of DQ3 prior
to and following each subsequent sector erase com-
mand. If DQ3 is high on the second status check, the
last command might not have been accepted.
Table 23 shows the status of DQ3 relative to the other
status bits.
Table 23.
Write Operation Status
Notes:
1. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits.
Refer to the section on DQ5 for more information.
2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details.
3. When reading write operation status bits, the system must always provide the bank address where the Embedded Algorithm
is in progress. The device outputs array data if the system addresses a non-busy bank.
4. The system may read either asynchronously or synchronously (burst) while in erase suspend.
5. The RDY pin acts a dedicated output to indicate the status of an embedded erase or program operation is in progress. This
is available in the Asynchronous mode only.
Status
DQ7
(Note 2)
DQ6
DQ5
(Note 1)
DQ3
DQ2
(Note 2)
RDY (Note
5)
Standard
Mode
Embedded Program Algorithm
DQ7#
Toggle
0
N/A
No toggle
0
Embedded Erase Algorithm
0
Toggle
0
1
Toggle
0
Erase
Suspend
Mode
Erase-Suspend-
Read (Note 4)
Erase
Suspended Sector
1
No toggle
0
N/A
Toggle
High
Impedance
Non-Erase
Suspended Sector
Data
Data
Data
Data
Data
High
Impedance
Erase-Suspend-Program
DQ7#
Toggle
0
N/A
N/A
0



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