PCF2103EUSLASH2SLASHF2 datasheet(6/56 Pages) PHILIPS

6 / 56 page

1998 May 11

Philips Semiconductors

Product speciﬁcation

LCD controllers/drivers

PCF2103 family

Table 1

Pin functions; note 1

Note

1. When the I2C-bus is used, the parallel interface pin E must be defined as E = 0. In I2C-bus read mode DB7 to DB0

should be connected to VDD or left open-circuit.

a) When the parallel bus is used, pins SCL and SDA must be connected to VSS or VDD; they may not be left

unconnected.

b) If the 4-bit interface is used without reading out from the PCF2103 (i.e. R/W is set permanently to logic 0), the

unused ports DB0 to DB3 can either be set to VSS or VDD instead of leaving them open.

NAME

FUNCTION

DESCRIPTION

RS selects the register to be accessed for read and write; there is an internal pull-up

on this pin

RS = 0 selects the instruction register for write and the busy flag and address

counter for read

RS = 1 selects the data register for both read and write

R/W

read/write

R/W selects either the read (R/W = 1) or write (R/W = 0) operation; there is an

internal pull-up on this pin

data bus clock

pin E is set HIGH to signal the start of a read or write operation; data is clocked in or

out of the chip on the negative edge of the clock

DB7 to DB0

data bus

the bi-directional, 3-state data bus transfers data between the system controller and

the PCF2103; DB7 may be used as the busy ﬂag, signalling that internal operations

are not yet completed; in 4-bit operations the 4 higher order lines DB7 to DB4 are

used; DB3 to DB0 must be left open-circuit; there is an internal pull-up on each of the

data lines

C1 to C60

column driver

outputs

these pins output the data for columns

R1 to R18

row driver

outputs

these pins output the row select waveforms to the display; R17 and R18 drive the

icons

VLCD

LCD power

supply

positive power supply for the liquid crystal display

OSC

oscillator

when the on-chip oscillator is used this pin must be connected to VDD; an external

clock signal, if used, is input at this pin

SCL

serial clock line

input for the I2C-bus clock signal

SDA

serial data line

I/O for the I2C-bus data line

SA0

address pin

the hardware sub-address line is used to program the device sub-address for two

different PCF2103s on the same I2C-bus

test pad

must be connected to VSS; not user accessible

power-down pad PD selects chip power-down mode; for normal operation PD = 0

PCF2103EU/2/F2 数据表(PDF) 6 Page - NXP Semiconductors

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