PCF2103EUSLASH2SLASHF2 datasheet(7/56 Pages) PHILIPS

7 / 56 page

1998 May 11

Philips Semiconductors

Product speciﬁcation

LCD controllers/drivers

PCF2103 family

FUNCTIONAL DESCRIPTION

7.1

LCD bias voltage generator

The intermediate bias voltages for the LCD display are generated on-chip. This removes the need for an external

resistive bias chain and significantly reduces the system current consumption. The optimum value of VLCD depends on

the multiplex rate, the LCD threshold voltage (Vth) and the number of bias levels and is given by the relationships given

in Tables 2 and 3. Using a 5-level bias scheme for 1 : 18 maximum rate allows VLCD <5 V for most LCD liquids.

Table 2

Optimum/maximum values for VOP (off pixels start darkening; Voff =Vth)

Table 3

Minimum values for VOP (on pixels clearly visible; Von >Vth)

MUX RATE

NUMBER OF LEVELS

Von/Vth

VOP/Vth

VOP (typical; for Vth = 1.4 V)

1 : 18

1.272

3.7

5.2 V

1 : 2

2.236

2.283

3.9 V

MUX RATE

NUMBER OF LEVELS

Von/Vth

VOP/Vth

VOP (typical; for Vth = 1.4 V)

1 : 18

1.12

3.2

4.6 V

1 : 2

1.2

1.5

2.1 V

7.2

Oscillator

The on-chip oscillator provides the clock signal for the

display system. No external components are required and

pin OSC must be connected to VDD.

7.3

External clock

If an external clock is to be used, it is input at the OSC pin.

The resulting display frame frequency is given by

Only in the power-down state is the clock allowed to be

stopped (OSC connected to VSS), otherwise the LCD is

frozen in a DC state.

7.4

Power-on reset

The on-chip power-on reset block initializes the chip after

power-on or power failure. This is a synchronous reset and

requires 3 oscillator cycles to be executed. Afterwards, a

clear display is initiated.

7.5

Power-down mode

The chip can be put into power-down mode where all static

currents are switched off (no internal oscillator, no bias

level generation, all LCD outputs are internally connected

to VSS) when PD = 1.

frame

osc

3072

-------------

During power-down, the whole chip is being reset and will

restart with a clear display after power-down. Therefore,

the whole chip has to be initialized after a power-down as

after an initial power-up.

7.6

Registers

The PCF2103 has two 8-bit registers, an Instruction

Select signal (RS) determines which register will be

accessed. The instruction register stores instruction codes

such as ‘display clear’ and ‘cursor shift’, and address

information for the Display Data RAM (DDRAM) and

Character Generator RAM (CGRAM). The instruction

controller. The data register temporarily stores data to be

read from the DDRAM and CGRAM. When reading, data

from the DDRAM or CGRAM corresponding to the address

in the instruction register is written to the data register prior

to being read by the ‘read data’ instruction.

7.7

Busy ﬂag

The busy flag indicates the internal status of the PCF2103.

Logic 1 indicates that the chip is busy and further

instructions will not be accepted. The busy flag is output at

pin DB7 when RS = 0 and R/W = 1. Instructions should

only be written after checking that the busy flag is logic 0

or waiting for the required number of cycles.

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