PCF2103EUSLASH2SLASHF2 datasheet(26/56 Pages) PHILIPS

26 / 56 page

1998 May 11

Philips Semiconductors

Product speciﬁcation

LCD controllers/drivers

PCF2103 family

8.12.5

SCREEN CONFIGURATION

The default value for L is logic 0. In the event of L = 0 the

two halves of a split screen are connected in a standard

way i.e. column 1/61, 2/62 to 60/120. In the event of L = 1

the two halves of a split screen are connected in a mirrored

way i.e. column 1/120, 2/119 to 60/61. This allows single

layer PCB or glass layout.

8.12.6

DISPLAY CONFIGURATION

The default value for P and Q is logic 0. P = 1 mirrors the

column data whereas Q = 1 mirrors the row data.

8.12.7

REDUCING CURRENT CONSUMPTION

Reducing current consumption can be achieved by one of

the options mentioned in Table 10.

Table 10 Reducing current consumption

ORIGINAL MODE

ALTERNATIVE MODE

Character mode

icon mode (control bit IM)

Display on

display off (control bit D)

INTERFACE TO MICROCONTROLLER

9.1

Parallel interface

The PCF2103 can send data in either two 4-bit operations

or one 8-bit operation and can thus interface to 4-bit or

8-bit microcontrollers.

In 8-bit mode data is transferred as 8-bit bytes using the

8 data lines DB7 to DB0. Three further control lines E, RS

and R/W are required; see Table 1.

In 4-bit mode data is transferred in two cycles of 4 bits

each using pins DB7 to DB4 for transaction. The higher

order bits (corresponding to DB7 to DB4 in 8-bit mode) are

sent in the first cycle and the lower order bits (DB3 to DB0

in 8-bit mode) in the second. Data transfer is complete

after two 4-bit data transfers. Note that two cycles are also

required for the busy flag check. 4-bit operation is selected

by instruction. See Figs 11 to 14 for examples of bus

protocol.

In 4-bit mode pins DB3 to DB0 must be left open-circuit.

They are pulled up to VDD internally.

PCF2103EU/2/F2 数据表(PDF) 26 Page - NXP Semiconductors

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