PCF2103EUSLASH2SLASHF2 datasheet(27/56 Pages) PHILIPS

27 / 56 page

1998 May 11

Philips Semiconductors

Product speciﬁcation

LCD controllers/drivers

PCF2103 family

9.2

I2C-bus interface

9.2.1

CHARACTERISTICS OF THE I2C-BUS

The I2C-bus is for bidirectional, two-line communication

between different ICs or modules. The two lines are a

serial data line (SDA) and a Serial Clock Line (SCL).

Both lines must be connected to a positive supply via a

pull-up resistor. Data transfer may be initiated only when

the bus is not busy.

Each byte of eight bits is followed by an acknowledge bit.

The acknowledge bit is a HIGH-level signal put on the bus

by the transmitter during which time the master generates

an extra acknowledge related clock pulse. A slave receiver

which is addressed must generate an acknowledge after

the reception of each byte. Also a master receiver must

generate an acknowledge after the reception of each byte

that has been clocked out of the slave transmitter.

The device that acknowledges must pull down the SDA

line during the acknowledge clock pulse, so that the SDA

line is stable LOW during the HIGH period of the

acknowledge related clock pulse (set-up and hold times

must be taken into consideration). A master receiver must

signal an end of data to the transmitter by not generating

an acknowledge on the last byte that has been clocked out

of the slave. In this event the transmitter must leave the

data line HIGH to enable the master to generate a STOP

condition.

9.2.2

I2C-BUS PROTOCOL

Before any data is transmitted on the I2C-bus, the device

which should respond is addressed first. The addressing is

always carried out with the first byte transmitted after the

start procedure. The I2C-bus configuration for the different

PCF2103 read and write cycles is shown in Figs 20 to 21.

The slow down feature of the I2C-bus protocol (receiver

holds SCL low during internal operations) is not used in the

PCF2103.

9.2.3

DEFINITIONS

• Transmitter: the device which sends the data to the bus

• Receiver: the device which receives the data from the

bus

• Master: the device which initiates a transfer, generates

clock signals and terminates a transfer

• Slave: the device addressed by a master

• Multi-master: more than one master can attempt to

control the bus at the same time without corrupting the

message

• Arbitration: procedure to ensure that, if more than one

master simultaneously tries to control the bus, only one

is allowed to do so and the message is not corrupted

• Synchronization: procedure to synchronize the clock

signals of two or more devices.

PCF2103EU/2/F2 数据表(PDF) 27 Page - NXP Semiconductors

PCF2103EU/2/F2 数据表(HTML) 27 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56

数据表下载