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PCF2103EU/2/F2 数据表(PDF) 35 Page - NXP Semiconductors

部件名 PCF2103EU/2/F2
功能描述  LCD controllers/drivers
PDF  56 Pages
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制造商  PHILIPS [NXP Semiconductors]
网页  http://www.nxp.com
标志 PHILIPS - NXP Semiconductors

PCF2103EU/2/F2 数据表(HTML) 35 Page - NXP Semiconductors

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1998 May 11
35
Philips Semiconductors
Product specification
LCD controllers/drivers
PCF2103 family
13 AC CHARACTERISTICS
VDD = 1.8 to 5.5 V; VSS =0V; VLCD = 2.2 − 6.5 V; Tamb = −40 to +85 °C; unless otherwise specified.
Note
1. All timing values are valid within the operating supply voltage and ambient temperature range and are referenced to
VIL and VIH with an input voltage swing of VSS to VDD.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
ffr(LCD)
LCD frame frequency (internal clock)
VDD = 5.0 V
45
81
147
Hz
fosc
oscillator frequency (not available at any pin)
140
250
450
kHz
fosc(ext)
external clock frequency
140
450
kHz
tOSCST
oscillator start-up time after PD going from
logic 1 to logic 0
200
300
µs
Bus timing characteristics: parallel interface; note 1
WRITE OPERATION (WRITING DATA FROM MICROCONTROLLER TO PCF2103); see Fig.23
Ten(cy)
enable cycle time
500
−−
ns
tW(en)
enable pulse width
220
−−
ns
tsu(A)
address set-up time
50
−−
ns
th(A)
address hold time
25
−−
ns
tsu(D)
data set-up time
60
−−
ns
th(D)
data hold time
25
−−
ns
READ OPERATION (READING DATA FROM PCF2103 TO MICROCONTROLLER); see Fig.24
Ten(cy)
enable cycle time
500
−−
ns
tW(en)
enable pulse width
220
−−
ns
tsu(A)
address set-up time
50
−−
ns
th(A)
address hold time
25
−−
ns
td(D)
data delay time
−−
150
ns
th(D)
data hold time
20
100
ns
Timing characteristics: I2C-bus interface; note 1
fSCL
SCL clock frequency
−−
400
kHz
tLOW
SCL clock LOW period
1.3
−−µs
tHIGH
SCL clock HIGH period
0.6
−−µs
tSU;DAT
data set-up time
100
−−
ns
tHD;DAT
data hold time
0
−−
ns
tr
SCL and SDA rise time
−−
300
ns
tf
SCL and SDA fall time
−−
300
ns
CB
capacitive bus line load
−−
400
pF
tSU;STA
set-up time for a repeated START condition
0.6
−−µs
tHD;STA
START condition hold time
0.6
−−µs
tSU;STO
set-up time for STOP condition
0.6
−−µs
tSW
tolerable spike width on bus
−−
50
ns



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