PCF2103EUSLASH2SLASHF2 datasheet(24/56 Pages) PHILIPS

24 / 56 page

1998 May 11

Philips Semiconductors

Product speciﬁcation

LCD controllers/drivers

PCF2103 family

8.8

Set DDRAM address

‘Set DDRAM address’ sets the DDRAM address ADD into

the address counter (binary A[6] to A[0]). Data can then be

written to or read from the DDRAM.

8.9

Read busy ﬂag and address counter

‘Read busy flag and address counter’ reads the Busy Flag

(BF) and Address Counter (AC). BF = 1 indicates that an

internal operation is in progress. The next instruction will

not be executed until BF = 0, so BF should be checked

before sending another instruction.

At the same time, the value of the address counter

expressed in binary A[6] to A[0] is read out. The address

counter is used by both CGRAM and DDRAM, and its

value is determined by the previous instruction.

8.10

Write data to CGRAM or DDRAM

‘Write data’ writes binary 8-bit data D[7] to D[0] to the

CGRAM or the DDRAM.

Whether the CGRAM or DDRAM is to be written into is

determined by the previous ‘set CGRAM address’ or ‘set

DDRAM address’ command. After writing, the address

automatically increments or decrements by 1, in

accordance with the entry mode. Only bits D[4] to D[0] of

CGRAM data are valid, bits D[7] to D[5] are ‘don’t care’.

8.11

Read data from CGRAM or DDRAM

‘Read data’ reads binary 8-bit data D[7] to D[0] from the

CGRAM or DDRAM.

The most recent ‘set address’ command determines

whether the CGRAM or DDRAM is to be read.

The ‘read data’ instruction gates the content of the Data

goes LOW again, internal operation increments (or

decrements) the AC and stores RAM data corresponding

to the new AC into the DR.

It should be noted that there are only three instructions that

update the Data Register (DR). These are:

• ‘set CGRAM address’

• ‘set DDRAM address’

• ‘read data’ from CGRAM or DDRAM.

Other instructions (e.g. ‘write data’, ‘cursor/display shift’,

‘clear display’, ‘return home’) do not modify the data

8.12

Extended function set instructions and

features

8.12.1

NEW INSTRUCTIONS

H = 1 sets the chip into alternate instruction set mode.

8.12.2

ICON CONTROL

The PCF2103 can drive up to 120 icons. See Fig.14 for

CGRAM to icon mapping.

8.12.3

When IM = 0 the chip is in character mode. In character

mode characters and icons are driven (mux 1 : 18).

When IM = 1 the chip is in icon mode. In icon mode only

the icons are driven (mux 1 : 2).

8.12.4

Icon blink control is independent of the cursor/character

blink function.

When IB = 0 icon blink is disabled. Icon data is stored in

CGRAM character 0 to 2 (3

× 8 × 5 = 120 bits for

120 icons).

When IB = 1 icon blink is enabled. In this case each icon is

controlled by two bits. Blink consists of two half phases

(corresponding to the cursor on and off phases called even

and odd phases hereafter).

Icon states for the even phase are stored in CGRAM

characters 0 to 2 (3

× 8 × 5 = 120 bits for 120 icons).

These bits also define the icon state when the icon blink is

not used.

Icon states for the odd phase are stored in CGRAM

character 4 to 6 (another 120 bits for the 120 icons). When

icon blink is disabled CGRAM characters 4 to 6 may be

used as normal CGRAM characters.

PCF2103EU/2/F2 数据表(PDF) 24 Page - NXP Semiconductors

PCF2103EU/2/F2 数据表(HTML) 24 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56

数据表下载