PCF5083HSLASHF2 datasheet(10/136 Pages) PHILIPS

10 / 136 page

1996 Oct 29

Philips Semiconductors

Objective speciﬁcation

GSM signal processing IC

PCF5083

VSS1

Ground I/O pin.

VDD1

100

Supply I/O pin.

HD4 to HD7

101 to 104 I/O

Host Interface data (3-state).

HR/W

105

Host Interface Write Enable.

HCEN_D

106

Host Interface Enable - DSP core (active LOW).

DTACK

107

Host port acknowledge - used as DTACK from DSP core (active LOW, open-drain

output).

SIXCLK

108

DSP serial input port X clock (CMOS level Schmitt trigger input).

SIXEN

109

DSP serial input port X enable.

SIXD

110

DSP serial input port X data.

SOXCLK

111

DSP serial output port X clock (CMOS level Schmitt trigger input).

VDD2

112

Supply core.

VSS2

113

Ground core.

SOXEN

114

DSP serial output port X enable.

SOXD

115

DSP serial output port X data (3-state).

CLK20M

116

19.5 MHz CMOS level output.

FRAME_INT

117

TDMA frame interrupt (active LOW, open drain output).

COMB_INT

118

Combined interrupt (active LOW, open drain output).

HIPR_INT

119

High Priority Interrupt (active LOW, open drain output).

CLK13M

120

13 MHz CMOS level output.

VSS1

121

Ground I/O pin.

VDD1

122

Supply I/O pin.

AFS

123

I/O

Audio Interface frame sync signal (3-state).

ACLK

124

I/O

Audio Interface Clock (3-state).

ADI

125

Audio Interface Data In, RS232 clock if enabled.

ADO

126

Audio Interface Data Out (3-state).

TSCK1

127

Test Clock 1 - tied to VSS during normal operation.

TSCK2

128

Test Clock 2 - tied to VDD2 during normal operation.

SYMBOL

I/O

DESCRIPTION

PCF5083H/F2 数据表(PDF) 10 Page - NXP Semiconductors

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