PCF5083HSLASHF2 datasheet(34/136 Pages) PHILIPS

34 / 136 page

1996 Oct 29

Philips Semiconductors

Objective speciﬁcation

GSM signal processing IC

PCF5083

Table 17 Select ﬂags in register IMCOUT_REG

The inhibit flag (INH) in IMCOUT_REG controls whether

the IMC operation is inhibited during a receive or transmit

burst indicated with PDRX2 or NPDTX2 active. If the INH

flag is set the IMC operation is delayed until PDRX2 and

NPDTX2 become inactive. If the INH flag is reset the two

lines are don’t care.

8.4.4

OPERATION MODES AND CONTROL REGISTERS

The characteristics of each channel are controlled using

the contents of the registers RFCTRL0_REG to

RFCTRL3_REG.

The interface is programmable, one of three timing modes

can be selected for every data transfer. For the exact

timing see Chapter 16. In Mode 3 the transmission of the

data registers associated with the control register is

disabled.

If there is a conflict between the different data channels,

data transmission is scheduled according to Table 22.

Table 18 RC-IF Interface Bus Control Registers

SEL0 SEL1 SEL2 SEL3

ACTIVE ENABLE LINE

RFSEN1

RFSEN2

RFSEN3

RFSEN4

BIT

FLAG

OPERATION

These two bits select the timing

mode, see Table 19.

6M0

SEL1

These two bits are used to assert

the enable lines RFEN1 to RFEN1,

see Table 21.

SEL0

These four bits form the address

ﬁeld.

2A2

1A1

0A0

Table 19 Selection of the RC-IF Interface timing modes

Note

1. The 16 or 21 data bits are transmitted MSB first

according to Table 20.

Table 20 RF-IC Interface data structure

Note

1. The 21 bits consist of D17 to D0 and A2 to A0.

Table 21 Selection of enable lines RFEN1 to RFEN4

Table 22 Order of priority

MODE

BITS

TRANSFERRED

RFE

ASSERTED

yes

Transmission of the corresponding

data registers is disabled.

MODE

BITS

TRANSFERRED

1ST BIT

LAST

BIT

0 and 1

21(1)

D17

IMC channel

D20

D15

SEL1

SEL0

ENABLE LINE ASSERTED

RFEN1

RFEN2

RFEN3

RFEN4

PRIORITY

TRANSMISSION

Highest

frequency setting

gain control DACOFF_REG

gain control DACON_REG

gain control xxGAIN_REG then

DACx_REG

Lowest

Immediate Control Channel

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