PCF5083HSLASHF2 datasheet(20/136 Pages) PHILIPS

20 / 136 page

1996 Oct 29

Philips Semiconductors

Objective speciﬁcation

GSM signal processing IC

PCF5083

8.2.3

OFF TIMER AND WATCHDOG TIMER

The hardware switch-off and Watchdog Timer are used to

power-down the mobile if the System Controller has lost

control for more than 8 seconds.

8.2.3.1

Watchdog Timer

After the reset signal RST is deactivated, the Watchdog

Timer starts to count. If the timer expires after 8 seconds,

the POWON output is set LOW. To prevent this occurring,

the System Controller must restart the timer periodically,

reading register HWCTRL_REG within 8 seconds after the

previous read operation. The Watchdog function is

enabled if DSPEN = TIMEN = LOW. The configuration

DSPEN = TIMEN = HIGH disables the Watchdog Timer.

All other settings are for debugging purposes.

8.2.3.2

OFF Timer

After the switch-off request (HWCTRL_INT activated via

LOWVOLT or ONKEY conditions), the OFF-Timer starts to

count. If the timer expires after 8 seconds, or if the System

Controller sets HWCTRL_REG[SWOFF] to a logic 1, the

POWON output is set LOW. The OFF-Timer cannot be

restarted with a read access to register HWCTRL_REG.

For some special purposes, e.g. if the battery charging

control is handled from the System Controller, the

OFF-Timer can be stopped after it was activated from

ONKEY or LOWVOLT. It then resumes its watchdog

function. The OFF-Timer is stopped with a write access to

has to be A5H. Other data values do not stop the

OFF-Timer.

It should be noted that:

• The OFF/Watchdog Timer is not restarted after a stop

operation

• If either the ONKEY or LOWVOLT line stays active after

a stop operation, it is again recognized after its 1 second

switch-off time-out or 62.5 ms debouncing period,

respectively.

8.3

Timing Generator

The Timing Generator provides TDMA timing and

power-down signals for the RF transmitter, RF receiver,

synthesizer and baseband interface IC.

The Timing Generator has three modes of operation to

control the mobile:

1. Normal mode: in this mode the mobile is fully active.

All ICs receive their operating voltage, the power

consumption is reduced by switching the ICs on and

off with their power-down inputs.

2. Sleep or Idle mode: in this mode the mobile is

switched on, but no call is active. The mobile will be

fully activated if a mobile originated call is requested

via the keyboard. Otherwise parts of the mobile are

activated from time to time to monitor incoming calls.

Outside these intervals all ICs can be switched off

under control of the PCF5083. In this mode the main

13 MHz clock is switched off. To maintain TDMA

timing alignment, the PCF5083 is running temporarily

on a slower clock frequency.

3. Reduced Sleep mode: this mode is equal to the

Sleep mode, except that the TDMA timing alignment is

maintained by the main 13 MHz clock.

In this chapter the following definitions are used:

• 1 bit (Bit) = 48 ×

s = 3.692

µs (

TDMA

frame)

• 1 quarterbit (QB) = 1⁄

4 Bit = 0.923 µs (

TDMA

frame)

• 1 timeslot (TS) = 625 QB = 0.576 ms (1⁄8 TDMA frame)

• 1 Burst = 1 TS

The term frame refers to a TDMA frame throughout this

section unless otherwise stated.

The Timing Generator consists of:

• The quarterbit counter (QBC) counting 5000 quarterbit

steps in one TDMA frame and running on 1.0833 MHz.

This clock is switched off during Sleep mode.

• The Timing Generator (TG) with output polarity and

mask registers.

• The sleep quarterbit counter (SQBC).

• The Sleep mode timing generator.

13000000

--------------------------

1250

-------------

5000

-------------

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