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PCF5083H/F2 数据表(PDF) 26 Page - NXP Semiconductors |
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PCF5083H/F2 数据表(HTML) 26 Page - NXP Semiconductors |
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26 / 136 page ![]() 1996 Oct 29 26 Philips Semiconductors Objective specification GSM signal processing IC PCF5083 8.3.2.3 Timing Generation To generate all burst types required to fulfil the GSM timing, it is necessary to combine and/or modify the basic receive and transmit burst sequences. For this purpose two registers MODE0_REG and MODE1_REG exist, containing some flags to control the burst timing. Both mode registers and the registers RXSTART_REG, TXSTART_REG and MONSTART_REG have an additional pipeline stage.The first register stage can be read or written by the SC. The second stage is used for timing generation. The pipelining operation is performed at QBC = 0 (together with the frame interrupt generation). Some flags inside the mode registers have a third pipelining stage to allow the generation of a MON burst which overlaps into the next frame. The System Controller must set up the registers within the frame before the programmed timing becomes active. Which register MODE0_REG or MODE1_REG is actually used is described in Table 11. MODE0_REG and MODE1_REG contain identical flags. Table 11 Mode Registers (MODE0_REG and MODE1_REG) Table 12 Register selection for the MON burst BIT FLAG DESCRIPTION 13 USEMODE MODE_REGx select. If USERMODE = 0; then switch to MODE_REG0 after the next frame. If USERMODE = 1; then switch to MODE_REG1 after the next frame. 12 DISFRAMENT Disable frame interrupt. If DISFRAMENT = 1; then the frame interrupt is disabled. 11 RXCAL RX calibration timing. If RXCAL = 1; then the RX calibration timing is generated. 10 TXLENGTH Register select. The state of this bit determines which registers are used for the TX burst. If TXLENGTH = 0; then registers TXBURST0_REG and TXKEY0_REG are used. If TXLENGTH = 1; then registers TXBURST1_REG and TXKEY1_REG are used. 9 MONLENGTH1 RXBURSTx_REG select. The state of these two bits determine which RXBURST register is used for the MON burst; see Table 12. 8 MONLENGTH0 7 RXLENGTH1 RXBURSTx_REG select. The state of these two bits determine which RXBURST register is used for the Rx burst; see Table 13. 6 RXLENGTH0 5 DTX DTX timing enable. If DTX = 1; then DTX timing is enabled. 4 SEND TX burst timing. If SEND = 1; the TX burst timing is generated. 3 RECON Receiver start-up. If RECON = 1, the receiver start-up sequence for the MON burst in the idle frame is generated. 2 RECMON MON burst timing. If RECMON = 1; the MON burst timing is generated. 1 RECTX Third level measurement. If RECTX = 1; then the MON burst timing during the TX timeslot for a third level measurements generated. 0 RECRX Rx burst timing. If RECRX = 1; the Rx burst timing is generated. MONLENGTH1 MONLENGTH0 REGISTER SELECTED 0 0 RXBURST0_REG is used. 0 1 RXBURST1_REG is used. 1 0 RXBURST2_REG is used. 1 1 Undefined during a MON burst. |
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