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PCF5083H/F2 数据表(PDF) 120 Page - NXP Semiconductors

部件名 PCF5083H/F2
功能描述  GSM signal processing IC
PDF  136 Pages
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制造商  PHILIPS [NXP Semiconductors]
网页  http://www.nxp.com
标志 PHILIPS - NXP Semiconductors

PCF5083H/F2 数据表(HTML) 120 Page - NXP Semiconductors

Back Button PCF5083H/F2 Datasheet HTML 116Page - NXP Semiconductors PCF5083H/F2 Datasheet HTML 117Page - NXP Semiconductors PCF5083H/F2 Datasheet HTML 118Page - NXP Semiconductors PCF5083H/F2 Datasheet HTML 119Page - NXP Semiconductors PCF5083H/F2 Datasheet HTML 120Page - NXP Semiconductors PCF5083H/F2 Datasheet HTML 121Page - NXP Semiconductors PCF5083H/F2 Datasheet HTML 122Page - NXP Semiconductors PCF5083H/F2 Datasheet HTML 123Page - NXP Semiconductors PCF5083H/F2 Datasheet HTML 124Page - NXP Semiconductors Next Button
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1996 Oct 29
120
Philips Semiconductors
Objective specification
GSM signal processing IC
PCF5083
Voice Port timing - non-transparent mode (see Fig.37 and note 14)
1(7)
AFS setup time to ACLK HIGH
200
−−
ns
2(7)
AFS hold time after ACLK LOW
10
−−
ns
3(7)
ADO hold time after ACLK HIGH
−
30
ns
4(7)
ADI setup time to ACLK LOW
30
−−
ns
5(7)
ADI hold time to ACLK LOW
40
−−
ns
6(7)
ACLK frequency
−−
1
MHz
7(7)
ACLK HIGH time
400
−−
ns
8(7)
ACLK LOW time
400
−−
ns
JTAG Port timing (see Fig.38)
1
TCK LOW time
35
−−
ns
2
TCK HIGH time
25
−−
ns
3
TCK cycle time
−−
10
ns
4
TMS setup time to TCK HIGH
10
−−
ns
5
TMS hold time after TCK HIGH
30
−−
ns
6
TDI setup time to TCK HIGH
5
−−
ns
7
TDI hold time after TCK HIGH
30
−−
ns
8
TDO asserted after TCK LOW
−−
60
ns
9
TDO hold time after TCK LOW
−−
60
ns
10
TDO 3-state after TCK LOW
−−
30
ns
11
TRSTN pulse width
100
−−
ns
General purpose parallel port (see Fig.39)
1
PIO data valid after CLK13M rising edge (output)
−
70
−
ns
2
PIO data setup time
−
10
−
ns
3
PIO data valid after CLK13M rising edge (input)
−
70
−
ns
All outputs
tr(7)
rise time
−−
20
ns
tf(7)
fall time
−−
20
ns
NO
PARAMETER
MIN.
TYP.
MAX.
UNIT



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