4LS5K datasheet(77/115 Pages) OSRAM

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4LS

Datasheet

• PUBLIC

DS000542

• v3-01 • 2022-Nov-17

114

│ 76

9.1.31

Status 5 Register (Address 0x1E)

Figure 129:

STS5Reg

Address: 0x1E

Default Value: 0x30

Access: Read/Write

Bit

Bit Name

Default

Bit Description

7:7

VREF CDS Buff Half

Current

When set to ‘1’ reduces the VREF CDS

buffer current to half.

6:6

VRST Pixel Buff Half

Current

When set to ‘1’ reduces the VRST pixel

buffer current to half.

5:4

CLK Phase

11b

It is used to choose between Rise-

Edge and Fall-Edge of MLCK to

perform the serializer synchronization.

3:2

PLL Resistor

00b

Increases the PLL resistor for

stabilization purposes.

1:0

PLL Charge Pump

00b

To be used to configure the current on

the PLL charge pump.

Figure 130:

Effect on MLCK Provided to Serializer of 4LS

CLK Phase

Bit 5

Bit 4

Effect on MLCK Provided to Serializer

Copy of MCLK

Inverted copy of MCLK

Copy of MCLK delayed by 1 PLL clock

Copy of MCLK delayed by 2 PLL clocks

Figure 131:

PLL Charge Pump Programmed by Register

Bit 1

Bit 0

Current [µA]

1.6

3.2

4.9

6.5

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