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4LS

Functional Description

Datasheet

• PUBLIC

DS000542

• v3-01 • 2022-Nov-17

114

│ 50

8-Bit mode @ 80 MHz

Below described is an example to calculate the maximum line rate for 8-bit mode, for the below

configuration. The region of interested is based on Figure 71.

●

Output mode: 8-bit

●

Readout mode: 1-To-1 LVDS

●

ADC response stabilization OFF

●

Auto-start AD OFF

●

Auto-start readout OFF

●

End of Range = 0x3F

For full resolution, it was verified that the minimum Readout Time is much higher than the ADC time,

therefore the maximum line rate was defined by the Readout Time. When performing a ROI in sensor,

the goal is to calculate how much the Readout Time can be decreased to achieve the highest line rate

possible.

Taking in consideration Equation 4, the MTA and maximum line rate as shown below:

Figure 73:

8-Bit Timing Clocks with ROI On for Readout Mode 1-To-1

– MTA Calculation

Parameters

Clocks

ADC Time

280

SAMPLE

START_AD

TBTW_START_AD&RST_RAMP

TBTW_SAMPLE&START_AD

DTI

112

MTA

335 => 238.8 kLines/s

Max Integration Time(1)

223 => 2787.5 ns

(1)

To use the sensor at the maximum line, this is the maximum integration time possible. When it comes to the minimum

integration time, in theory, it is possible to use a lower integration time, but it was not tested on this configuration. From

an application perspective, using a lower integration time, does not bring significant advantages, once the line rate

cannot be higher and the system would need to increase the illumination power.

Now the Readout Time needs to be calculated in order to achieve the respective line rate and

guarantee the minimum LVAL Low Period.

●

Start Region of Interest Register Segment A = 0x54 = 84d

●

Start Region of Interest Register Segment B = 0x00

●

End Region of interest Register Segment A = 0xA0 = 160d

●

End Region of Interest Register Segment B = 0x4C = 76d

�� = ((160 − 84) + 1) × (4 × 1)) = 308 ��

�� = 308 + 26 = 334 ��

4LS5K 数据表(PDF) 51 Page - OSRAM GmbH

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