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4LS

Functional Description

Datasheet

• PUBLIC

DS000542

• v3-01 • 2022-Nov-17

114

│ 34

Figure 47:

Number of Words Sent for Valid Training Sequence

Number of Outputs

VTS @ 8-Bit Mode

Each Word is 8-Bit

VTS @ 12-Bit Mode

Each Word is 12-Bit

4 Outputs (1-To-1)

1 x TSB + 11 x (TSA + TSB) = 23 Words = 23 x TMCLK

2 Outputs (2-To-1)

1 x TSB + 13 x (TSA+ TSB) = 27 Words = 27 x TMCLK

1 Output (4-To-1)

1 x TSB + 17 x (TSA + TSB) = 35 Words = 35 x TMCLK

The TS number of words will depend on the pixel timing applied, having a minimum value of three

clocks, so the LVAL low period has a minimum of 26, 30 and 38 clocks, for the readout modes of 1-

To-1, 2-To-1 and 4-To-1, respectively. This margin of three clocks has to be guaranteed in the pixel

timing, in order to avoid timing violations.

Equation 1:

��_�� (��) = �� + ��

Figure 48:

Minimum LVAL Low Period (Clocks)

Number of Outputs

VTS (clocks)

Minimum TS (clocks)

Minimum LVAL Low

Period (clocks)

4 Outputs (1-To-1)

2 Outputs (2-To-1)

1 Output (4-To-1)

When performing a synchronization of the serializer to the chip main clock, the phase and bit

information gathered from the training sequences must be newly acquired. If the synchronization of

the serializer is performed with each start of readout (this can be controlled over register 0x01, bit 4),

only the transmission at the beginning of each line of data should be considered as valid.

7.10

Output Mode and Data Transmission

By configuration means it is possible to reduce the number of output taps per line from 2-To-1 (half of

LVDS channels) and 4-To-1 (a quarter of LVDS channels). This permits to read the entire lines only by

two taps per line, or one tap per line, respectively. However when using this option, the readout speed

will be reduced to approximately ½ or ¼ relative to the default 1-To-1 readout mode speed (using four

output taps), respectively. It is approximate because the VTS are slightly different between readout

modes.

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