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4LS

Functional Description

Datasheet

• PUBLIC

DS000542

• v3-01 • 2022-Nov-17

114

│ 49

12-Bit mode @ 60 MHz

Below described is an example to calculate the maximum line rate for 12-bit mode:

●

Output mode: 12-bit

●

Readout mode: 1-To-1 LVDS

●

ADC response stabilization OFF

●

Auto-start AD OFF

●

Auto-start readout OFF

●

End of Range = 0xFF

●

Start Region on Interest Register = 0x20

●

End Region of interest Register = 0x90

�� = ((144 − 32) + 1) × (4 × 1) = 452 ��

�� = 476 + 26 = 468 ��

�� = 4 × 452 = 1808 ��

�� = 1808 + 1808 = 3616 ��

Figure 72:

12-Bit Timing Clocks with ROI On

Parameters

Clocks

RST_CDS

ADC Time

707

Readout Data

452

Readout Time

468

SAMPLE

START_AD

TBTW_START_AD&RST_RAMP

TBTW_SAMPLE&START_AD

FCT

748

MTA => Line Rate

748 => 80.21 kHz

DTI

Max Integration Time

680 => 11.33 µs

Minimum LVALLow_Period

296

The minimum LVAL time at low between two consecutive data streams is:

��_�� = 748 − 452 = 296 ��

Using ROI feature for 12-bit mode, in terms of line rate, it does not bring any advantage, because the

ADC time is still much higher than the readout time.

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