XCB56364PV100 datasheet(24/148 Pages) FREESCALE

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Reset, Stop, Mode Select, and Interrupt Timing

DSP56364 Technical Data, Rev. 4.1

3-8

Freescale Semiconductor

Delay from WR assertion to interrupt request deassertion

for level sensitive fast interrupts6, 7

• DRAM for all WS

(WS + 3.5)

× T

C – 10.94

—

• SRAM WS = 1

(WS + 3.5)

× T

C – 10.94

—

• SRAM WS = 2, 3

(WS + 3)

× T

C – 10.94

—

•SRAM WS

≥ 4

(WS + 2.5)

× T

C – 10.94

—

Duration for IRQA assertion to recover from Stop state

5.9

—

Delay from IRQA assertion to fetch of first instruction (when

exiting Stop)3, 8

• PLL is not active during Stop (PCTL Bit 17 = 0) and Stop

delay is enabled (OMR Bit 6 = 0)

PLC

× ET

C × PDF +

(128 K

− PLC/2) × T

1.3

13.6

• PLL is not active during Stop (PCTL Bit 17 = 0) and Stop

delay is not enabled (OMR Bit 6 = 1)

PLC

× ET

C × PDF +

(23.75

± 0.5) × T

232.5

12.3

• PLL is active during Stop (PCTL Bit 17 = 1) (Implies No

Stop Delay)

(8.25

± 0.5) × T

77.5

87.5

Duration of level sensitive IRQA assertion to ensure

interrupt service (when exiting Stop)3, 8

• PLL is not active during Stop (PCTL Bit 17 = 0) and Stop

delay is enabled (OMR Bit 6 = 0)

PLC

× ET

C × PDF +

(128 K

− PLC/2) × T

13.6

—

• PLL is not active during Stop (PCTL Bit 17 = 0) and Stop

delay is not enabled (OMR Bit 6 = 1)

PLC

× ET

C × PDF +

(20.5

± 0.5) × T

12.3

—

• PLL is active during Stop (PCTL Bit 17 = 1) (implies no

Stop delay)

5.5

× T

55.0

—

Interrupt Requests Rate

• ESAI, SCI

12TC

—

120.0

•DMA

8TC

—80.0

•

IRQ, NMI (edge trigger)

8TC

—80.0

•

IRQ, NMI (level trigger)

12TC

—

120.0

DMA Requests Rate

• Data read from ESAI, SCI

6TC

—60.0

• Data write to ESAI, SCI

7TC

—70.0

•

IRQ, NMI (edge trigger)

3TC

—30.0

Table 3-7 Reset, Stop, Mode Select, and Interrupt Timing1 (continued)

No.

Characteristics

Expression2

Min

Max

Unit

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