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XCB56364PV100 数据表(PDF) 36 Page - Freescale Semiconductor, Inc

部件名 XCB56364PV100
功能描述  24-Bit Audio Digital Signal Processor
PDF  148 Pages
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制造商  FREESCALE [Freescale Semiconductor, Inc]
网页  http://www.freescale.com
标志 FREESCALE - Freescale Semiconductor, Inc

XCB56364PV100 数据表(HTML) 36 Page - Freescale Semiconductor, Inc

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External Memory Expansion Port (Port A)
DSP56364 Technical Data, Rev. 4.1
3-20
Freescale Semiconductor
Table 3-10 DRAM Page Mode Timings, Two Wait States1, 2, 3, 4
No.
Characteristics
Symbol
Expression5
66 MHz
80 MHz
Unit
Min
Max
Min
Max
131
Page mode cycle time for two consecutive
accesses of the same direction
tPC
2
× T
C
45.4
37.5
ns
Page mode cycle time for mixed (read and
write) accesses
1.25
× T
C
41.1
34.4
ns
132
CAS assertion to data valid (read)
tCAC
1.5
× T
C − 7.5
15.2
ns
1.5
× T
C − 6.5
12.3
ns
133
Column address valid to data valid (read)
tAA
2.5
× T
C − 7.5
30.4
ns
2.5
× T
C − 6.5
24.8
ns
134
CAS deassertion to data not valid (read hold
time)
tOFF
0.0
0.0
ns
135
Last CAS assertion to RAS deassertion
tRSH
1.75
× T
C − 4.0
22.5
17.9
ns
136
Previous CAS deassertion to RAS
deassertion
tRHCP
3.25
× T
C − 4.0
45.2
36.6
ns
137
CAS assertion pulse width
tCAS
1.5
× T
C − 4.0
18.7
14.8
ns
138
Last CAS deassertion to RAS deassertion6
• BRW[1:0] = 00
tCRP
2.0
× T
C − 6.0
24.4
19.0
ns
• BRW[1:0] = 01
3.5
× T
C − 6.0
47.2
37.8
ns
• BRW[1:0] = 10
4.5
× T
C − 6.0
62.4
50.3
ns
• BRW[1:0] = 11
6.5
× T
C − 6.0
92.8
75.3
ns
139
CAS deassertion pulse width
tCP
1.25
× T
C − 4.0
14.9
11.6
ns
140
Column address valid to CAS assertion
tASC
TC − 4.0
11.2
8.5
ns
141
CAS assertion to column address not valid
tCAH
1.75
× T
C − 4.0
22.5
17.9
ns
142
Last column address valid to RAS
deassertion
tRAL
3
× T
C − 4.0
41.5
33.5
ns
143
WR deassertion to CAS assertion
tRCS
1.25
× T
C − 3.8
15.1
11.8
ns
144
CAS deassertion to WR assertion
tRCH
0.5
× T
C − 3.7
3.9
2.6
ns
145
CAS assertion to WR deassertion
tWCH
1.5
× T
C − 4.2
18.5
14.6
ns
146
WR assertion pulse width
tWP
2.5
× T
C − 4.5
33.5
26.8
ns



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