XCB56364PV100 datasheet(20/148 Pages) FREESCALE

20 / 148 page

AC Electrical Characteristics

DSP56364 Technical Data, Rev. 4.1

3-4

Freescale Semiconductor

3.5

AC Electrical Characteristics

The timing waveforms shown in the AC electrical characteristics section are tested with a VIL maximum

of 0.3 V and a VIH minimum of 2.4 V for all pins except EXTAL, which is tested using the input levels

shown in Note 8 of the previous table. AC timing specifications, which are referenced to a device input

signal, are measured in production with respect to the 50% point of the respective input signal’s transition.

DSP56364 output levels are measured with the production test machine VOL and VOH reference levels set

at 0.4 V and 2.4 V, respectively.

NOTE

Although the minimum value for the frequency of EXTAL is 0 MHz, the

device AC test conditions are 15 MHz and rated speed.

3.6

Internal Clocks

5 This characteristic does not apply to PCAP.

Section 5, "Design Considerations" provides a formula to compute the estimated current requirements in Normal

mode. In order to obtain these results, all inputs must be terminated (i.e., not allowed to float). Measurements are based on

synthetic intensive DSP benchmarks. The power consumption numbers in this specification are 90% of the measured results

of this benchmark. This reflects typical DSP applications. Typical internal supply current is measured with VCC = 3.3 V at TJ

= 105°C. Maximum internal supply current is measured with VCC = 3.46 V at TJ = 105°C.

7 In order to obtain these results, all inputs must be terminated (i.e., not allowed to float). PLL signal is disabled during Stop

state.

8 In order to obtain these results, all inputs, which are not disconnected at Stop mode, must be terminated (i.e., not allowed to

float).

Table 3-4 Internal Clocks

Characteristics

Symbol

Expression1, 2

Min

Typ

Max

Internal operation frequency with PLL enabled

—

(Ef

× MF)/

(PDF

× DF)

—

Internal operation frequency with PLL disabled

—

Ef/2

—

Internal clock high period

• With PLL disabled

—

ETC

—

• With PLL enabled and MF

≤ 40.49 × ET

C ×

PDF

× DF/MF

—0.51

× ET

C ×

PDF

× DF/MF

• With PLL enabled and MF > 4

0.47

× ET

C ×

PDF

× DF/MF

—0.53

× ET

C ×

PDF

× DF/MF

XCB56364PV100 数据表(PDF) 20 Page - Freescale Semiconductor, Inc

XCB56364PV100 数据表(HTML) 20 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载

链接网址

XCB56364PV100 数据表(PDF) 20 Page - Freescale Semiconductor, Inc

XCB56364PV100 数据表(HTML) 20 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表 下载

链接网址

数据表下载