数据搜索系统,热门电子元器件搜索
  Chinese  ▼
ALLDATASHEETCN.COM

X  

XCB56364PV100 数据表(PDF) 34 Page - Freescale Semiconductor, Inc

部件名 XCB56364PV100
功能描述  24-Bit Audio Digital Signal Processor
PDF  148 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
制造商  FREESCALE [Freescale Semiconductor, Inc]
网页  http://www.freescale.com
标志 FREESCALE - Freescale Semiconductor, Inc

XCB56364PV100 数据表(HTML) 34 Page - Freescale Semiconductor, Inc

Back Button XCB56364PV100 Datasheet HTML 30Page - Freescale Semiconductor, Inc XCB56364PV100 Datasheet HTML 31Page - Freescale Semiconductor, Inc XCB56364PV100 Datasheet HTML 32Page - Freescale Semiconductor, Inc XCB56364PV100 Datasheet HTML 33Page - Freescale Semiconductor, Inc XCB56364PV100 Datasheet HTML 34Page - Freescale Semiconductor, Inc XCB56364PV100 Datasheet HTML 35Page - Freescale Semiconductor, Inc XCB56364PV100 Datasheet HTML 36Page - Freescale Semiconductor, Inc XCB56364PV100 Datasheet HTML 37Page - Freescale Semiconductor, Inc XCB56364PV100 Datasheet HTML 38Page - Freescale Semiconductor, Inc Next Button
Zoom Inzoom in Zoom Outzoom out
 34 / 148 page
background image
External Memory Expansion Port (Port A)
DSP56364 Technical Data, Rev. 4.1
3-18
Freescale Semiconductor
134
CAS deassertion to data not valid
(read hold time)
tOFF
0.0
0.0
ns
135
Last CAS assertion to RAS
deassertion
tRSH
0.75
× T
C − 4.0
33.5
21.0
ns
136
Previous CAS deassertion to RAS
deassertion
tRHCP
2
× T
C − 4.0
96.0
62.7
ns
137
CAS assertion pulse width
tCAS
0.75
× T
C − 4.0
33.5
21.0
ns
138
Last CAS deassertion to RAS
deassertion5
BRW[1:0] = 00
tCRP
1.75
× T
C − 6.0
81.5
52.3
ns
• BRW[1:0] = 01
3.25
× T
C − 6.0
156.5
102.2
ns
• BRW[1:0] = 10
4.25
× T
C − 6.0
206.5
135.5
ns
• BRW[1:0] = 11
6.25
× T
C – 6.0
306.5
202.1
ns
139
CAS deassertion pulse width
tCP
0.5
× T
C − 4.0
21.0
12.7
ns
140
Column address valid to CAS
assertion
tASC
0.5
× T
C − 4.0
21.0
12.7
ns
141
CAS assertion to column address not
valid
tCAH
0.75
× T
C − 4.0
33.5
21.0
ns
142
Last column address valid to RAS
deassertion
tRAL
2
× T
C − 4.0
96.0
62.7
ns
143
WR deassertion to CAS assertion
tRCS
0.75
× T
C − 3.8
33.7
21.2
ns
144
CAS deassertion to WR assertion
tRCH
0.25
× T
C − 3.7
8.8
4.6
ns
145
CAS assertion to WR deassertion
tWCH
0.5
× T
C − 4.2
20.8
12.5
ns
146
WR assertion pulse widt
h
tWP
1.5
× T
C − 4.5
70.5
45.5
ns
147
Last WR assertion to RAS deassertion
tRWL
1.75
× T
C − 4.3
83.2
54.0
ns
148
WR assertion to CAS deassertion
tCWL
1.75
× T
C − 4.3
83.2
54.0
ns
149
Data valid to CAS assertion (Write)
tDS
0.25
× T
C − 4.0
8.5
4.3
ns
150
CAS assertion to data not valid (write)
tDH
0.75
× T
C − 4.0
33.5
21.0
ns
151
WR assertion to CAS assertion
tWCS
TC − 4.3
45.7
29.0
ns
Table 3-9 DRAM Page Mode Timings, One Wait State (Low-Power Applications)1, 2, 3 (continued)
No.
Characteristics
Symbol
Expression
20 MHz4
30 MHz4
Unit
Min
Max
Min
Max



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100  ...More


数据表 下载

Go To PDF Page


链接网址



ALLDATASHEET是否为您带来帮助?  [ DONATE ] 

关于 Alldatasheet   |   广告服务   |   联系我们   |   隐私政策   |   数据表链接    |   链接交换   |   制造商名单
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com