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XCB56364PV100 数据表(PDF) 30 Page - Freescale Semiconductor, Inc |
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XCB56364PV100 数据表(HTML) 30 Page - Freescale Semiconductor, Inc |
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30 / 148 page  External Memory Expansion Port (Port A) DSP56364 Technical Data, Rev. 4.1 3-14 Freescale Semiconductor 108 Data valid to WR deassertion (data setup time) tDS (tDW)(WS − 0.25) × TC − 3.0 [WS ≥ 1] 4.5 — ns 109 Data hold time from WR deassertion tDH 0.25 × T C − 2.0 [1 ≤ WS ≤ 3] 0.5 — ns 1.25 × T C − 2.0 [4 ≤ WS ≤ 7] 10.5 — ns 2.25 × T C − 2.0 [WS ≥ 8] 20.5 — ns 113 RD deassertion time 0.75 × T C − 4.0 [1 ≤ WS ≤ 3] 3.5 — ns 1.75 × T C − 4.0 [4 ≤ WS ≤ 7] 13.5 — ns 2.75 × T C − 4.0 [WS ≥ 8] 23.5 — ns 114 WR deassertion time 0.5 × T C − 4.0 [WS = 1] 1.0 — ns TC − 2.0 [2 ≤ WS ≤ 3] 6.0 — ns 2.5 × T C − 4.0 [4 ≤ WS ≤ 7] 21.0 — ns 3.5 × T C − 4.0 [WS ≥ 8] 31.0 — ns 115 Address valid to RD assertion 0.5 × T C − 4.0 1.0 — ns 116 RD assertion pulse width (WS + 0.25) × T C −4.0 8.5 — ns 117 RD deassertion to address not valid 0.25 × T C − 2.0 [1 ≤ WS ≤ 3] 0.5 — ns 1.25 × T C − 2.0 [4 ≤ WS ≤ 7] 10.5 — ns 2.25 × T C − 2.0 [WS ≥ 8] 20.5 — ns Table 3-8 SRAM Read and Write Accesses1 (continued) No. Characteristics Symbol Expression2 Min Max Unit |
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