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XCB56364PV100 数据表(PDF) 49 Page - Freescale Semiconductor, Inc |
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XCB56364PV100 数据表(HTML) 49 Page - Freescale Semiconductor, Inc |
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49 / 148 page  External Memory Expansion Port (Port A) DSP56364 Technical Data, Rev. 4.1 Freescale Semiconductor 3-33 191 RD assertion to RAS deassertion tROH 11.5 × T C − 4.0 111.0 — ns 192 RD assertion to data valid tGA 10 × T C − 7.0 — 93.0 ns 193 RD deassertion to data not valid3 tGZ 0.0 — ns 194 WR assertion to data active 0.75 × T C − 0.3 7.2 — ns 195 WR deassertion to data high impedance 0.25 × T C —2.5 ns 1 The number of wait states for out-of-page access is specified in the DCR. 2 The refresh period is specified in the DCR. 3 RD deassertion will always occur after CAS deassertion; therefore, the restricted timing is t OFF and not tGZ. 4 The asynchronous delays specified in the expressions are valid for DSP56364. 5 Either t RCH or tRRH must be satisfied for read cycles. Table 3-16 DRAM Out-of-Page and Refresh Timings, Fifteen Wait States1, 2 No. Characteristics3 Symbol Expression Min Max Unit 157 Random read or write cycle time tRC 16 × T C 160.0 — ns 158 RAS assertion to data valid (read) tRAC 8.25 × T C − 5.7 — 76.8 ns 159 CAS assertion to data valid (read) tCAC 4.75 × T C − 5.7 — 41.8 ns 160 Column address valid to data valid (read) tAA 5.5 × T C − 5.7 — 49.3 ns 161 CAS deassertion to data not valid (read hold time) tOFF 0.0 0.0 — ns 162 RAS deassertion to RAS assertion tRP 6.25 × T C − 4.0 58.5 — ns 163 RAS assertion pulse width tRAS 9.75 × T C − 4.0 93.5 — ns 164 CAS assertion to RAS deassertion tRSH 6.25 × T C − 4.0 58.5 — ns 165 RAS assertion to CAS deassertion tCSH 8.25 × T C − 4.0 78.5 — ns 166 CAS assertion pulse width tCAS 4.75 × T C − 4.0 43.5 — ns 167 RAS assertion to CAS assertion tRCD 3.5 × T C ± 2 33.0 37.0 ns 168 RAS assertion to column address valid tRAD 2.75 × T C ± 2 25.5 29.5 ns 169 CAS deassertion to RAS assertion tCRP 7.75 × T C − 4.0 73.5 — ns 170 CAS deassertion pulse width tCP 6.25 × T C − 4.0 58.5 — ns 171 Row address valid to RAS assertion tASR 6.25 × T C − 4.0 58.5 — ns 172 RAS assertion to row address not valid tRAH 2.75 × T C − 4.0 23.5 — ns Table 3-15 DRAM Out-of-Page and Refresh Timings, Eleven Wait States1, 2 (continued) No. Characteristics3 Symbol Expression4 Min Max Unit |
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