XCB56364PV100 datasheet(8/148 Pages) FREESCALE

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Clock and PLL

DSP56364 Technical Data, Rev. 4.1

2-4

Freescale Semiconductor

2.4

Clock and PLL

2.5

External Memory Expansion Port (Port A)

When the DSP56364 enters a low-power standby mode (stop or wait), it tri-states the relevant port A

signals: D0–D7, AA0, AA1, RD, WR, CAS.

2.5.1

External Address Bus

GNDC (1)

Bus Control Ground—GNDC is an isolated ground for the bus control I/O drivers. This connection must

be tied externally to all other chip ground connections. The user must provide adequate external decoupling

capacitors. There is one GNDC connections.

GNDS (3)

SHI and ESAI —GNDS is an isolated ground for the SHI and ESAI. This connection must be tied externally

to all other chip ground connections. The user must provide adequate external decoupling capacitors.

There are three GNDS connections.

Table 2-4 Clock and PLL Signals

Signal Name

Type

State During

Reset

Signal Description

EXTAL

Input

External Clock Input—An external clock source must be connected to EXTAL in

order to supply the clock to the internal clock generator and PLL.

PCAP

Input

PLL Capacitor—PCAP is an input connecting an off-chip capacitor to the PLL filter.

Connect one capacitor terminal to PCAP and the other terminal to VCCP.

If the PLL is not used, PCAP may be tied to VCC, GND, or left floating.

PINIT/NMI

Input

PLL Initial/Nonmaskable Interrupt—During assertion of RESET, the value of

PINIT/NMI is written into the PLL Enable (PEN) bit of the PLL control register,

determining whether the PLL is enabled or disabled. After RESET de assertion and

during normal instruction processing, the PINIT/NMI Schmitt-trigger input is a

negative-edge-triggered nonmaskable interrupt (NMI) request internally

synchronized to internal system clock.

This input is 5 V tolerant.

Table 2-5 External Address Bus Signals

Signal Name

Type

State During

Reset

Signal Description

A0–A17

Output

Keeper active Address Bus—A0–A17 are active-high outputs that specify the address for

external program and data memory accesses. Otherwise, the signals are kept

to their previous values by internal weak keepers. To minimize power

dissipation, A0–A17 do not change state when external memory spaces are not

being accessed.

Table 2-3 Grounds (continued)

Ground Name

Description

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