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TVP7002PZP 数据表(PDF) 31 Page - Texas Instruments |
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TVP7002PZP 数据表(HTML) 31 Page - Texas Instruments |
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31 / 52 page ![]() www.ti.com Sync Separator Threshold H-PLL Pre-Coast H-PLL Post-Coast TVP7002 SLES206 – MAY 2007 Subaddress 11h Default (20h) 7 6 5 4 3 2 1 0 Sync Separator Threshold [7:0] Sync Separator Threshold [7:0]: Sets how many internal clock reference periods the sync separator counts to before toggling high or low. Sync Separator Threshold [7:0] × (minimum clock period) must be greater than the width of the negative sync pulse. This setting can also affect the position of the VSOUT. See register 22h. Note: The internal clock reference is typically 6.3 MHz, but a minimum clock period of 133 ns is recommended to allow for clock variation. Subaddress 12h Default (00h) 7 6 5 4 3 2 1 0 Pre-Coast [7:0] Pre-Coast [7:0]: Sets the number of HSYNC periods that coast becomes active prior to VSYNC leading edge. Subaddress 13h Default (00h) 7 6 5 4 3 2 1 0 Post-Coast [7:0] Post-Coast [7:0]: Sets the number of HSYNC periods that coast stays active following VSYNC trailing edge. Post-Coast settings must be extended to include Macrovision pseudo syncs when Macrovision is present. Table 11. Recommended H-PLL Pre-Coast and H-PLL Post-Coast Settings STANDARD H-PLL PRE_COAST H-PLL POST-COAST 480i/p with Macrovision 3 0Ch 576i/p with Macrovision 3 0Ch 1080i 0 0 1080p 0 0 720p 0 0 31 Submit Documentation Feedback |
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