TVP7002PZP datasheet(5/52 Pages) TI

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TVP7002

SLES206 – MAY 2007

TERMINAL FUNCTIONS

TERMINAL

I/O

DESCRIPTION

NAME

NO.

ANALOG VIDEO

RIN_1

Analog video input for R/Pr 1

RIN_2

Analog video input for R/Pr 2

RIN_3

Analog video input for R/Pr 3

GIN_1

Analog video input for G/Y 1

GIN_2

100

Analog video input for G/Y 2

GIN_3

Analog video input for G/Y 3

GIN_4

Analog video input for G/Y 4

BIN_1

Analog video input for B/Pb 1

BIN_2

Analog video input for B/Pb 2

BIN_3

Analog video input for B/Pb 3

The inputs must be AC coupled. The recommended coupling capacitor is 0.1

µF. Unused analog

inputs should be connected to ground using a 10-nF capacitor.

CLOCK SIGNALS

DATACLK

Data clock output

EXT_CLK

External clock input. May be used as a timing reference for the mode detection block instead of

the internal clock reference. May also be used as the ADC sample clock instead of the H-PLL

generated clock.

DIGITAL VIDEO

ROUT[9:0]

55–59, 61–65

Digital video output of R/Cr, ROUT[9] is the most-significant bit (MSB).

GOUT[9:0]

43-52

Digital video output of G/Y, GOUT[9] is the MSB.

BOUT[9:0]

29-38

Digital video output of B/Cb, BOUT[9] is the MSB.

For 4:2:2 mode, multiplexed CbCr data is output on BOUT[9:0].

Unused outputs can be left unconnected.

MISCELLANEOUS SIGNALS

PWDN

Power down input

0 = Normal mode

1 = Power down

RESETB

Reset input, active low. Outputs are placed in a high-impedance mode during reset (see

Table 8).

TMS

Test mode select input, active high. Used to enable scan test mode. For normal operation,

connect to ground.

FILT1

External filter connection for the horizontal PLL. A 0.1-

µF capacitor in series with a 1.5-kΩ

resistor should be connected from this pin to pin 89 (see Figure 4).

FILT2

External filter connection for the horizontal PLL. A 4.7-nF capacitor should be connected from

this pin to pin 89 (see Figure 4).

PLL_F

Horizontal PLL filter internal supply connection

HOST INTERFACE

I2CA

I2C slave address input. Has internal pulldown resistor (see Table 7).

0 = Slave address = B8h

1 = Slave address = BAh

SCL

I2C clock input

SDA

I/O

I2C data bus

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