TVP7002PZP datasheet(23/52 Pages) TI

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Power Up, Reset, and Initialization

Power

Reset

I C

5 ms

1 µs

TVP7002

SLES206 – MAY 2007

No specific power-up sequence is required, but all power supplies should be active and stable within 500 ms of

each other. Reset may be low during power up, but must remain low for at least 1

µs after the power supplies

become stable. Alternatively, reset may be asserted any time with minimum 5-ms delay after power-up and must

remain asserted for at least 1

µs. Reset timing is shown in Figure 7. It is also recommended that any I2C

operation starts 1

µs after reset ended. Table 8 describes the status of the TVP7002 terminals during and

immediately after reset.

Table 8. Output Mode Per Reset Sequence State

OUTPUT MODE

SIGNAL NAME

DURING RESET

RESET COMPLETED

Default Condition

ROUT[9:0], BOUT[9:0], GOUT[9:0]

High impedance

(see bit 0 of subaddress

17h)

Default Condition

HSOUT, VSOUT, FIDOUT, DATACLK

High impedance

(see bit 0 of subaddress

17h)

Default Condition

SOGOUT

High impedance

(see bit 1 of subaddress

17h)

Figure 7. Reset Timing

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