ADC3908CSSS datasheet(117/131 Pages) TI1

117 / 131 page

7.2.3 Application Curves

The following FFT plots show the performance of THS4541 driving the ADC3910D125 operated at 125MSPS

with a full-scale input at -1dBFS.

Input Frequency (MHz)

-120

-100

-80

-60

-40

-20

AIN = - 1dBFS, SNR = 60dBFS, SFDR = 56dBFS

Figure 7-2. 5MHz FFT (THS4541 FDA)

Input Frequency (MHz)

-120

-100

-80

-60

-40

-20

AIN = - 1dBFS, SNR = 60dBFS, SFDR = 52dBFS

Figure 7-3. 10MHz FFT (THS4541 FDA)

7.3 Initialization Set Up

After power-up, the internal registers must be initialized to their default values through a hardware reset by

applying a high pulse on the RESET pin.

1. Apply AVDD and IOVDD (no specific sequence required). After AVDD is applied the internal band gap

reference powers up and settle out in approximately 2ms.

2. Apply hardware reset. After hardware reset is released, the default registers are loaded from internal fuses

and the internal power up capacitor calibration is initiated. The calibration takes approximately 200000 clock

cycles.

3. Begin programming using SPI interface.

7.3.1 Register Initialization During Operation

If required, the serial interface registers can be cleared and reset to default settings during operation either:

• Through a hardware reset or

• By applying a software reset. When using the serial interface, set the RESET bit (register address 0x00) high.

This setting initializes the internal registers to the default values, and then self-resets the RESET bit low. In

this case, the RESET pin is kept low.

After hardware or software reset the wait time is also approximately 200000 clock cycles before the SPI registers

can be programmed.

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ADC3910D025, ADC3910D065, ADC3910D125

ADC3910S025, ADC3910S065, ADC3910S125

SBASAD1A – DECEMBER 2023 – REVISED MAY 2024

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Product Folder Links: ADC3910D025 ADC3910D065 ADC3910D125 ADC3910S025 ADC3910S065 ADC3910S125

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