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ADC3908CSSS 数据表(PDF) 120 Page - Texas Instruments |
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ADC3908CSSS 数据表(HTML) 120 Page - Texas Instruments |
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120 / 131 page  7.5.2 Layout Example The following screen shot shows the top layer of the ADC3910D125EVM. • Signal inputs are routed as different signal and along with clock input on the top layer avoiding vias. • Serial CMOS output interface lanes with isolation resistor. • Bypass caps are close to the VREF pin on the top layer avoiding vias. Clock routing without vias Analog inputs routed on top layer with no vias CMOS output lines with isolation resistors Bypass caps close to VREF pin Figure 7-7. Layout Example: top layer of ADC3910D125EVM ADC3910D025, ADC3910D065, ADC3910D125 ADC3910S025, ADC3910S065, ADC3910S125 SBASAD1A – DECEMBER 2023 – REVISED MAY 2024 www.ti.com 120 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated Product Folder Links: ADC3910D025 ADC3910D065 ADC3910D125 ADC3910S025 ADC3910S065 ADC3910S125 |
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