PIC18F258-ESLASHSOSQTP datasheet(42/402 Pages) MICROCHIP

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PIC18FXX8

DS41159E-page 40

4.2.3

PUSH AND POP INSTRUCTIONS

Since the Top-of-Stack (TOS) is readable and writable,

the ability to push values onto the stack and pull values

off the stack, without disturbing normal program execu-

tion, is a desirable option. To push the current PC value

onto the stack, a PUSH instruction can be executed.

This will increment the Stack Pointer and load the

current PC value onto the stack. TOSU, TOSH and

TOSL can then be modified to place a return address

on the stack.

The POP instruction discards the current TOS by decre-

menting the Stack Pointer. The previous value pushed

onto the stack then becomes the TOS value.

4.2.4

STACK FULL/UNDERFLOW RESETS

These Resets are enabled by programming the

STVREN configuration bit. When the STVREN bit is

disabled, a full or underflow condition will set the appro-

priate STKFUL or STKUNF bit, but not cause a device

Reset. When the STVREN bit is enabled, a full or

underflow condition will set the appropriate STKFUL or

STKUNF bit and then cause a device Reset. The

STKFUL or STKUNF bits are only cleared by the user

software or a POR.

4.3

Fast Register Stack

A “fast return” option is available for interrupts and

calls. A fast register stack is provided for the Status,

WREG and BSR registers and is only one layer in

depth. The stack is not readable or writable and is

loaded with the current value of the corresponding

The values in the fast register stack are then loaded

back into the working registers if the FAST RETURN

instruction is used to return from the interrupt.

A low or high priority interrupt source will push values

into the stack registers. If both low and high priority

interrupts are enabled, the stack registers cannot be

used reliably for low priority interrupts. If a high priority

interrupt occurs while servicing a low priority interrupt,

the stack register values stored by the low priority

interrupt will be overwritten.

If high priority interrupts are not disabled during low

priority interrupts, users must save the key registers in

software during a low priority interrupt.

If no interrupts are used, the fast register stack can be

used to restore the Status, WREG and BSR registers at

the end of a subroutine call. To use the fast register

stack for a subroutine call, a FAST CALL instruction

must be executed.

Example 4-1 shows a source code example that uses

the fast register stack.

EXAMPLE 4-1:

FAST REGISTER STACK

CODE EXAMPLE

4.4

PCL, PCLATH and PCLATU

The Program Counter (PC) specifies the address of the

instruction to fetch for execution. The PC is 21 bits

wide. The low byte is called the PCL register. This reg-

ister is readable and writable. The high byte is called

the PCH register. This register contains the PC<15:8>

bits and is not directly readable or writable. Updates to

the PCH register may be performed through the

PCLATH register. The upper byte is called PCU. This

readable or writable. Updates to the PCU register may

be performed through the PCLATU register.

The PC addresses bytes in the program memory. To

prevent the PC from becoming misaligned with word

instructions, the LSb of PCL is fixed to a value of ‘0’.

The PC increments by 2 to address sequential

instructions in the program memory.

The CALL,

RCALL,

GOTO

and program branch

instructions write to the program counter directly. For

these instructions, the contents of PCLATH and

PCLATU are not transferred to the program counter.

The contents of PCLATH and PCLATU will be

transferred to the program counter by an operation that

writes PCL. Similarly, the upper two bytes of the

program counter will be transferred to PCLATH and

PCLATU by an operation that reads PCL. This is useful

for computed offsets to the PC (see Section 4.8.1

“Computed GOTO”).

CALL SUB1, FAST

;STATUS, WREG, BSR

;SAVED IN FAST REGISTER

;STACK

•

SUB1

•

RETURN FAST

;RESTORE VALUES SAVED

;IN FAST REGISTER STACK

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