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PIC18F258-E/SOSQTP 数据表(PDF) 52 Page - Microchip Technology |
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PIC18F258-E/SOSQTP 数据表(HTML) 52 Page - Microchip Technology |
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52 / 402 page  PIC18FXX8 DS41159E-page 50 © 2006 Microchip Technology Inc. TMR1H Timer1 Register High Byte xxxx xxxx 31, 116 TMR1L Timer1 Register Low Byte xxxx xxxx 31, 116 T1CON RD16 — T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0-00 0000 31, 113 TMR2 Timer2 Register 0000 0000 31, 118 PR2 Timer2 Period Register 1111 1111 31, 118 T2CON — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 31, 117 SSPBUF SSP Receive Buffer/Transmit Register xxxx xxxx 31, 146 SSPADD SSP Address Register in I2C™ Slave mode. SSP Baud Rate Reload Register in I2C Master mode. 0000 0000 31, 152 SSPSTAT SMP CKE D/A PS R/W UA BF 0000 0000 31, 144, 153 SSPCON1 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 31, 145, 145 SSPCON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 0000 0000 31, 155 ADRESH A/D Result Register High Byte xxxx xxxx 31, 243 ADRESL A/D Result Register Low Byte xxxx xxxx 31, 243 ADCON0 ADCS1 ADCS0 CHS2 CHS1 CHS0 GO/DONE —ADON 0000 00-0 31, 241 ADCON1 ADFM ADCS2 — — PCFG3 PCFG2 PCFG1 PCFG0 00-- 0000 32, 242 CCPR1H Capture/Compare/PWM Register 1 High Byte xxxx xxxx 32, 124 CCPR1L Capture/Compare/PWM Register 1 Low Byte xxxx xxxx 32, 124 CCP1CON — — DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 32, 123 ECCPR1H(1) Enhanced Capture/Compare/PWM Register 1 High Byte xxxx xxxx 32, 133 ECCPR1L(1) Enhanced Capture/Compare/PWM Register 1 Low Byte xxxx xxxx 32, 133 ECCP1CON(1) EPWM1M1 EPWM1M0 EDC1B1 EDC1B0 ECCP1M3 ECCP1M2 ECCP1M1 ECCP1M0 0000 0000 32, 131 ECCP1DEL(1) EPDC7 EPDC6 EPDC5 EPDC4 EPDC3 EPDC2 EPDC1 EPDC0 0000 0000 32, 140 ECCPAS(1) ECCPASE ECCPAS2 ECCPAS1 ECCPAS0 PSSAC1 PSSAC0 PSSBD1 PSSBD0 0000 0000 32, 142 CVRCON(1) CVREN CVROE CVRR CVRSS CVR3 CVR2 CVR1 CVR0 0000 0000 32, 255 CMCON(1) C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0 0000 0000 32, 249 TMR3H Timer3 Register High Byte xxxx xxxx 32, 121 TMR3L Timer3 Register Low Byte xxxx xxxx 32, 121 T3CON RD16 T3ECCP1 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON 0000 0000 32, 119 SPBRG USART Baud Rate Generator 0000 0000 32, 185 RCREG USART Receive Register 0000 0000 32, 191 TXREG USART Transmit Register 0000 0000 32, 189 TXSTA CSRC TX9 TXEN SYNC — BRGH TRMT TX9D 0000 -010 32, 183 RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 32, 184 EEADR EEPROM Address Register xxxx xxxx 32, 59 EEDATA EEPROM Data Register xxxx xxxx 32, 59 EECON2 EEPROM Control Register 2 (not a physical register) xxxx xxxx 32, 59 EECON1 EEPGD CFGS — FREE WRERR WREN WR RD xx-0 x000 32, 60, 67 IPR3 IRXIP WAKIP ERRIP TXB2IP TXB1IP TXB0IP RXB1IP RXB0IP 1111 1111 32, 90 PIR3 IRXIF WAKIF ERRIF TXB2IF TXB1IF TXB0IF RXB1IF RXB0IF 0000 0000 32, 84 PIE3 IRXIE WAKIE ERRIE TXB2IE TXB1IE TXB0IE RXB1IE RXB0IE 0000 0000 32, 87 IPR2 —CMIP — EEIP BCLIP LVDIP TMR3IP ECCP1IP(1) -1-1 1111 32, 89 PIR2 —CMIF — EEIF BCLIF LVDIF TMR3IF ECCP1IF(1) -0-0 0000 32, 83 PIE2 —CMIE — EEIE BCLIE LVDIE TMR3IE ECCP1IE(1) -0-0 0000 32, 86 TABLE 4-2: REGISTER FILE SUMMARY (CONTINUED) File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Details on Page: Legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition Note 1: These registers or register bits are not implemented on the PIC18F248 and PIC18F258 and read as ‘0’s. 2: Bit 21 of the TBLPTRU allows access to the device configuration bits. 3: RA6 and associated bits are configured as port pins in RCIO and ECIO Oscillator mode only and read ‘0’ in all other oscillator modes. |
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